diff --git a/.cproject b/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..efb1c675513d7b546108f57426d9c558c3af5dff
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,128 @@
+
+
+
+
+
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+
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+
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diff --git a/.project b/.project
new file mode 100644
index 0000000000000000000000000000000000000000..16a4b9f2a05b569980a12348b0202224259d9298
--- /dev/null
+++ b/.project
@@ -0,0 +1,33 @@
+
+
+ Lab0
+
+
+
+
+
+ com.freescale.processorexpert.core.expertprojectbuilder
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.freescale.processorexpert.core.expertprojectnature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/.settings/com.freescale.processorexpert.core.prefs b/.settings/com.freescale.processorexpert.core.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..e9beb854b96cf01add3af2d457760748de90fefa
--- /dev/null
+++ b/.settings/com.freescale.processorexpert.core.prefs
@@ -0,0 +1,21 @@
+#
+# Please do not modify or delete this file
+#
+eclipse.preferences.version=1
+DERIVATIVE_NAME=MK70FN1M0xxx12
+PE_FAMILY=Kinetis
+PE_CPE_FILE=MCU10
+PE_MODE=CLASSIC
+LANGUAGE=c
+LANGUAGE_POSSIBILITIES=${com.processorexpert.wizard.language.c} ${com.processorexpert.wizard.language.asm}
+COMPILER=GNU C Compiler
+VARIANTS=MK70FN1M0VMJ12
+CONFIGURATIONS=RAM;FLASH
+PROJECT_NAME=ProcessorExpert
+INIT_ALL_PERIPHS=NO
+INIT_PINSETTINGS=NO
+STANDALONE=STANDALONE
+SDK_PROJECT=NO
+SDK_PATH=C:\Freescale\KSDK_1.2.0
+MQX_LITE=NO
+BOARD_NAME=${ProcessorBoard}
diff --git a/.settings/com.freescale.processorexpert.derivative.prefs b/.settings/com.freescale.processorexpert.derivative.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..f222c70bce769967de3309cb91ff1dbd9d068553
--- /dev/null
+++ b/.settings/com.freescale.processorexpert.derivative.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+versionGenerated/versionGenerated=1.0.0.RT7_b1515-0427
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
new file mode 100644
index 0000000000000000000000000000000000000000..31c305e8ec4fcda921260afa131299723a8a95c6
--- /dev/null
+++ b/.settings/language.settings.xml
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..fe13b550b3b741e5926089a75e82e1ab3e470e61
--- /dev/null
+++ b/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,67 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.codan.checkers.errnoreturn=Warning
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue=Error
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.checkers.noreturn=Error
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
diff --git a/.settings/org.eclipse.cdt.core.prefs b/.settings/org.eclipse.cdt.core.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..e8de000c8e79de09707e1361de89b136ee544369
--- /dev/null
+++ b/.settings/org.eclipse.cdt.core.prefs
@@ -0,0 +1,163 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18
+org.eclipse.cdt.core.formatter.alignment_for_assignment=16
+org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=80
+org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16
+org.eclipse.cdt.core.formatter.alignment_for_compact_if=16
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=34
+org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18
+org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0
+org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
+org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
+org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
+org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=16
+org.eclipse.cdt.core.formatter.alignment_for_member_access=0
+org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16
+org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=18
+org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16
+org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line_shifted
+org.eclipse.cdt.core.formatter.brace_position_for_block=next_line_shifted
+org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line_shifted
+org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
+org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line_shifted
+org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
+org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1
+org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true
+org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=true
+org.eclipse.cdt.core.formatter.compact_else_if=true
+org.eclipse.cdt.core.formatter.continuation_indentation=2
+org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2
+org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false
+org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true
+org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=true
+org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=true
+org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=true
+org.eclipse.cdt.core.formatter.indent_empty_lines=false
+org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true
+org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true
+org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true
+org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=true
+org.eclipse.cdt.core.formatter.indentation.size=2
+org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_after_template_declaration=insert
+org.eclipse.cdt.core.formatter.insert_new_line_at_end_of_file_if_missing=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_catch_in_try_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_closing_brace_in_array_initializer=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_colon_in_constructor_initializer_list=do not insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_else_in_if_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_identifier_in_function_declaration=insert
+org.eclipse.cdt.core.formatter.insert_new_line_before_while_in_do_statement=insert
+org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block=insert
+org.eclipse.cdt.core.formatter.insert_space_after_assignment_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_after_binary_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_brace_in_block=insert
+org.eclipse.cdt.core.formatter.insert_space_after_closing_paren_in_cast=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_base_clause=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_conditional=insert
+org.eclipse.cdt.core.formatter.insert_space_after_colon_in_labeled_statement=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_expression_list=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_throws=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments=insert
+org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_parameters=insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_arguments=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_parameters=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer=insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_bracket=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_cast=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_catch=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_parenthesized_expression=do not insert
+org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_switch=do not insert
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+org.eclipse.cdt.core.formatter.insert_space_after_semicolon_in_for=insert
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+org.eclipse.cdt.core.formatter.insert_space_before_assignment_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_before_binary_operator=insert
+org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_arguments=do not insert
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+org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
+org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
+org.eclipse.cdt.core.formatter.join_wrapped_lines=true
+org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false
+org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false
+org.eclipse.cdt.core.formatter.lineSplit=80
+org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1
+org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true
+org.eclipse.cdt.core.formatter.tabulation.char=mixed
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diff --git a/.settings/org.eclipse.cdt.ui.prefs b/.settings/org.eclipse.cdt.ui.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..68cdc88c84c84619fdc2fa5ded2e2b6fed9b8645
--- /dev/null
+++ b/.settings/org.eclipse.cdt.ui.prefs
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+formatter_profile=org.eclipse.cdt.ui.default.gnu_profile
+formatter_settings_version=1
diff --git a/.settings/org.eclipse.ltk.core.refactoring.prefs b/.settings/org.eclipse.ltk.core.refactoring.prefs
new file mode 100644
index 0000000000000000000000000000000000000000..cfcd1d3c22f7ad061b0ffb72377bff737ba31120
--- /dev/null
+++ b/.settings/org.eclipse.ltk.core.refactoring.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false
diff --git a/Debug/objects.mk b/Debug/objects.mk
new file mode 100644
index 0000000000000000000000000000000000000000..bf79edcfb799ac95f3f59eb215acfa8a3bc51632
--- /dev/null
+++ b/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS := -lLab0
+
diff --git a/Debug/sources.mk b/Debug/sources.mk
new file mode 100644
index 0000000000000000000000000000000000000000..b69fb0eee123c86d775373aaba8a720329cdc5f8
--- /dev/null
+++ b/Debug/sources.mk
@@ -0,0 +1,30 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+O_SRCS :=
+CPP_SRCS :=
+C_UPPER_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+CXX_SRCS :=
+C++_SRCS :=
+CC_SRCS :=
+C++_DEPS :=
+OBJS :=
+C_DEPS :=
+ASM_DEPS :=
+CC_DEPS :=
+CPP_DEPS :=
+CXX_DEPS :=
+C_UPPER_DEPS :=
+S_UPPER_DEPS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Sources \
+Project_Settings/Startup_Code \
+Generated_Code \
+
diff --git a/Documentation/Lab0_Settings.xml b/Documentation/Lab0_Settings.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ff6dcd5be202fb10b5d844281384700fe472c0c1
--- /dev/null
+++ b/Documentation/Lab0_Settings.xml
@@ -0,0 +1,220 @@
+
+
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diff --git a/Generated_Code/Cpu.c b/Generated_Code/Cpu.c
new file mode 100644
index 0000000000000000000000000000000000000000..8be2de4d0f7cfd0489a93569471bfb312be4991c
--- /dev/null
+++ b/Generated_Code/Cpu.c
@@ -0,0 +1,588 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : Cpu.c
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : MK70FN1M0MJ15
+** Version : Component 01.028, Driver 01.04, CPU db: 3.00.000
+** Repository : Kinetis
+** Datasheet : K70P256M150SF3RM, Rev. 2, Dec 2011
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+**
+** Settings :
+** Component name : Cpu
+** CPU type : MK70FN1M0VMJ12
+** CPU : CPU
+** MemModelDev : MemModel_NoFlexMem
+** Clock settings :
+** Internal oscillator :
+** Slow internal reference clock [kHz] : 32.768
+** Initialize slow trim value : no
+** Fast internal reference clock [MHz] : 4
+** Initialize fast trim value : no
+** RTC oscillator : Disabled
+** System oscillator 0 : Disabled
+** System oscillator 1 : Disabled
+** Clock source settings : 1
+** Clock source setting 0 :
+** Internal reference clock :
+** MCGIRCLK clock : Enabled
+** MCGIRCLK in stop : Disabled
+** MCGIRCLK source : Slow
+** MCGIRCLK clock [MHz] : 0.032768
+** External reference clock :
+** OSC0ERCLK clock : Enabled
+** OSC0ERCLK in stop : Disabled
+** OSC0ERCLK clock [MHz] : 0
+** OSC1ERCLK clock : Enabled
+** OSC1ERCLK in stop : Disabled
+** OSC1ERCLK clock [MHz] : 0
+** ERCLK32K clock source : System oscillator 0
+** ERCLK32K. clock [kHz] : 0
+** MCG settings :
+** MCG mode : FEI
+** MCG output clock : FLL clock
+** MCG output [MHz] : 20.97152
+** MCG external ref. clock source : System oscillator 0
+** MCG external ref. clock [MHz] : 0
+** Clock monitor :
+** System oscillator 0 : Disabled
+** RTC oscillator : Disabled
+** System oscillator 1 : Disabled
+** FLL settings :
+** FLL module : Enabled
+** FLL output [MHz] : 20.97152
+** MCGFFCLK clock [kHz] : 16.384
+** Reference clock source : Slow internal clock
+** FLL reference clock [kHz] : 32.768
+** Multiplication factor : Auto select
+** PLL 0 settings :
+** PLL module : Disabled
+** PLL module in Stop : Disabled
+** External reference select : System oscillator 0
+** PLL output [MHz] : 0
+** Reference clock divider : Auto select
+** PLL reference clock [MHz] : 1
+** Multiplication factor : Auto select
+** Loss of lock interrupt : Disabled
+** PLL 1 settings :
+** PLL module : Disabled
+** PLL module in Stop : Disabled
+** PLL output [MHz] : 0
+** External reference select : System oscillator 0
+** Reference clock divider : Auto select
+** PLL reference clock [MHz] : 1
+** Multiplication factor : Auto select
+** Loss of lock interrupt : Disabled
+** Initialization priority : minimal priority
+** Watchdog disable : yes
+** Internal peripherals :
+** NMI pin : Disabled
+** Reset control : Enabled
+** Reset pin : RESET_b
+** Reset pin signal :
+** Filter in STOP : Disabled
+** Filter in RUN/WAIT : Disabled
+** Filter width : 1
+** Debug interface (JTAG) :
+** JTAG Mode : JTAG
+** TDI : Enabled
+** TDI Pin : TSI0_CH2/PTA1/UART0_RX/FTM0_CH6/JTAG_TDI/EZP_DI
+** TDI Pin signal :
+** TDO : Enabled
+** TDO Pin : TSI0_CH3/PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO
+** TDO Pin signal :
+** TCK : Enabled
+** TCK Pin : TSI0_CH1/PTA0/UART0_CTS_b/UART0_COL_b/FTM0_CH5/JTAG_TCLK/SWD_CLK/EZP_CLK
+** TCK Pin signal :
+** TMS : Enabled
+** TMS Pin : TSI0_CH4/PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO
+** TMS Pin signal :
+** nTRST : Disabled
+** Flash memory organization :
+** Flash blocks : 4
+** Flash block 0 : PFlash
+** Address : 0x0
+** Size : 262144
+** Write unit size : 8
+** Erase unit size : 4096
+** Protection unit size : 32768
+** Flash block 1 : PFlash
+** Address : 0x40000
+** Size : 262144
+** Write unit size : 8
+** Erase unit size : 4096
+** Protection unit size : 32768
+** Flash block 2 : PFlash
+** Address : 0x80000
+** Size : 262144
+** Write unit size : 8
+** Erase unit size : 4096
+** Protection unit size : 32768
+** Flash block 3 : PFlash
+** Address : 0xC0000
+** Size : 262144
+** Write unit size : 8
+** Erase unit size : 4096
+** Protection unit size : 32768
+** Flexible memory controller : Disabled
+** Flash configuration field : Enabled
+** Security settings :
+** Flash security : Disabled
+** Freescale failure analysis access : Enabled
+** Mass erase : Enabled
+** Backdoor key security : Disabled
+** Backdoor key 0 : 255
+** Backdoor key 1 : 255
+** Backdoor key 2 : 255
+** Backdoor key 3 : 255
+** Backdoor key 4 : 255
+** Backdoor key 5 : 255
+** Backdoor key 6 : 255
+** Backdoor key 7 : 255
+** Protection regions :
+** P-Flash protection settings :
+** Protection region size : 32768
+** P-Flash protection : 0xFFFFFFFF
+** Protection regions :
+** Protection region 0 : Unprotected
+** Protection region 1 : Unprotected
+** Protection region 2 : Unprotected
+** Protection region 3 : Unprotected
+** Protection region 4 : Unprotected
+** Protection region 5 : Unprotected
+** Protection region 6 : Unprotected
+** Protection region 7 : Unprotected
+** Protection region 8 : Unprotected
+** Protection region 9 : Unprotected
+** Protection region 10 : Unprotected
+** Protection region 11 : Unprotected
+** Protection region 12 : Unprotected
+** Protection region 13 : Unprotected
+** Protection region 14 : Unprotected
+** Protection region 15 : Unprotected
+** Protection region 16 : Unprotected
+** Protection region 17 : Unprotected
+** Protection region 18 : Unprotected
+** Protection region 19 : Unprotected
+** Protection region 20 : Unprotected
+** Protection region 21 : Unprotected
+** Protection region 22 : Unprotected
+** Protection region 23 : Unprotected
+** Protection region 24 : Unprotected
+** Protection region 25 : Unprotected
+** Protection region 26 : Unprotected
+** Protection region 27 : Unprotected
+** Protection region 28 : Unprotected
+** Protection region 29 : Unprotected
+** Protection region 30 : Unprotected
+** Protection region 31 : Unprotected
+** D-Flash protection settings :
+** Protection region size :
+** D-Flash protection : 0xFF
+** Protection regions :
+** Protection region 0 : Unprotected
+** Protection region 1 : Unprotected
+** Protection region 2 : Unprotected
+** Protection region 3 : Unprotected
+** Protection region 4 : Unprotected
+** Protection region 5 : Unprotected
+** Protection region 6 : Unprotected
+** Protection region 7 : Unprotected
+** Eeprom protection settings :
+** Protection region size :
+** Eeprom protection : 0xFF
+** Protection regions :
+** Protection region 0 : Unprotected
+** Protection region 1 : Unprotected
+** Protection region 2 : Unprotected
+** Protection region 3 : Unprotected
+** Protection region 4 : Unprotected
+** Protection region 5 : Unprotected
+** Protection region 6 : Unprotected
+** Protection region 7 : Unprotected
+** Peripheral settings :
+** EzPort operation at boot : Enabled
+** Low power boot : Disabled
+** MPU settings : Enabled
+** MPU module : Disabled
+** AXBS settings : Disabled
+** AIPS0 settings : Disabled
+** AIPS1 settings : Disabled
+** MCM settings : Disabled
+** System control block settings : Disabled
+** Power management controller :
+** LVD reset : Enabled
+** LVD voltage treshold : Low
+** LVW voltage treshold : Low
+** Bandgap buffer : Disabled
+** LVD interrupt :
+** Interrupt : INT_LVD_LVW
+** Interrupt request : Disabled
+** Interrupt priority : 0 (Highest)
+** LVD interrupt : Disabled
+** LVW interrupt : Disabled
+** System Integration Module :
+** CLKOUT pin control : Disabled
+** CMT/UART pad drive strength : Single-pad drive
+** Clock gating control : Disabled
+** CPU interrupts/resets :
+** NMI interrupt : Disabled
+** Hard Fault : Disabled
+** Bus Fault : Disabled
+** Usage Fault : Disabled
+** Supervisor Call : Disabled
+** Pendable Service : Disabled
+** MCG : Disabled
+** DDR module : Disabled
+** External Bus : Disabled
+** Low power mode settings :
+** Allowed power modes :
+** Very low power modes : Not allowed
+** Low leakage stop mode : Not allowed
+** Very low leakage stop mode : Not allowed
+** LLWU settings : Disabled
+** Operation mode settings :
+** WAIT operation mode :
+** Return to wait after ISR : no
+** SLEEP operation mode :
+** Return to stop after ISR : no
+** STOP operation mode : Disabled
+** Clock configurations : 1
+** Clock configuration 0 :
+** __IRC_32kHz : 0.032768
+** __IRC_4MHz : 2
+** __SYSTEM_OSC : 8
+** __OSC1 : 8
+** __RTC_OSC : 0
+** Very low power mode : Disabled
+** Clock source setting : configuration 0
+** MCG mode : FEI
+** MCG output [MHz] : 20.97152
+** MCGIRCLK clock [MHz] : 0.032768
+** OSCERCLK clock [MHz] : 0
+** ERCLK32K. clock [kHz] : 0
+** MCGFFCLK [kHz] : 16.384
+** System clocks :
+** Core clock prescaler : Auto select
+** Core clock : 20.97152
+** Bus clock prescaler : Auto select
+** Bus clock : 20.97152
+** External clock prescaler : Auto select
+** External bus clock : 10.48576
+** Flash clock prescaler : Auto select
+** Flash clock : 10.48576
+** PLL/FLL clock selection : FLL
+** Clock frequency [MHz] : 20.97152
+** Contents :
+** No public methods
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file Cpu.c
+** @version 01.04
+** @brief
+**
+*/
+/*!
+** @addtogroup Cpu_module Cpu module documentation
+** @{
+*/
+
+/* MODULE Cpu. */
+
+/* {Default RTOS Adapter} No RTOS includes */
+#include "PE_Types.h"
+#include "PE_Error.h"
+#include "PE_Const.h"
+#include "IO_Map.h"
+#include "Cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Global variables */
+volatile uint8_t SR_reg; /* Current value of the FAULTMASK register */
+volatile uint8_t SR_lock = 0x00U; /* Lock */
+
+/*
+** ===================================================================
+** Method : Cpu_SetBASEPRI (component MK70FN1M0MJ15)
+**
+** Description :
+** This method sets the BASEPRI core register.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+void Cpu_SetBASEPRI(uint32_t Level);
+
+/*
+** ===================================================================
+** Method : Cpu_Cpu_Interrupt (component MK70FN1M0MJ15)
+**
+** Description :
+** This ISR services an unused interrupt/exception vector.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+PE_ISR(Cpu_Interrupt)
+{
+ /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
+ PE_DEBUGHALT();
+}
+
+
+/*** !!! Here you can place your own code using property "User data declarations" on the build options tab. !!! ***/
+
+/*lint -esym(765,__init_hardware) Disable MISRA rule (8.10) checking for symbols (__init_hardware). The function is linked to the EWL library */
+/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
+void __init_hardware(void)
+{
+
+ /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
+
+ /*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/
+ /*** PE initialization code after reset ***/
+ SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
+ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+ WDOG_STCTRLH_WAITEN_MASK |
+ WDOG_STCTRLH_STOPEN_MASK |
+ WDOG_STCTRLH_ALLOWUPDATE_MASK |
+ WDOG_STCTRLH_CLKSRC_MASK |
+ 0x0100U;
+
+ /* System clock initialization */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+ SIM_CLKDIV1_OUTDIV2(0x01) |
+ SIM_CLKDIV1_OUTDIV3(0x03) |
+ SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
+ if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
+ /* PMC_REGSC: ACKISO=1 */
+ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
+ }
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
+ SIM_CLKDIV1_OUTDIV2(0x00) |
+ SIM_CLKDIV1_OUTDIV3(0x01) |
+ SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
+ /* SIM_SOPT2: PLLFLLSEL=0 */
+ SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL(0x03)); /* Select FLL as a clock source for various peripherals */
+ /* SIM_SOPT1: OSC32KSEL=0 */
+ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL_MASK); /* System oscillator drives 32 kHz clock for various peripherals */
+ /* SIM_SCGC1: OSC1=1 */
+ SIM_SCGC1 |= SIM_SCGC1_OSC1_MASK;
+ /* Switch to FEI Mode */
+ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG_C1 = MCG_C1_CLKS(0x00) |
+ MCG_C1_FRDIV(0x00) |
+ MCG_C1_IREFS_MASK |
+ MCG_C1_IRCLKEN_MASK;
+ /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG_C2 = MCG_C2_RANGE0(0x00);
+ /* MCG_C4: DMX32=0,DRST_DRS=0 */
+ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+ /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0_CR = OSC_CR_ERCLKEN_MASK;
+ /* MCG_C10: LOCRE2=0,??=0,RANGE1=0,HGO1=0,EREFS1=0,??=0,??=0 */
+ MCG_C10 = MCG_C10_RANGE1(0x00);
+ /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC1_CR = OSC_CR_ERCLKEN_MASK;
+ /* MCG_C7: OSCSEL=0 */
+ MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
+ /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
+ MCG_C5 = MCG_C5_PRDIV0(0x00);
+ /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG_C6 = MCG_C6_VDIV0(0x00);
+ /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
+ MCG_C11 = MCG_C11_PRDIV1(0x00);
+ /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
+ MCG_C12 = MCG_C12_VDIV1(0x00); /* 3 */
+ while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+ /*** End of PE initialization code after reset ***/
+
+ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
+
+}
+
+/*
+** ===================================================================
+** Method : Cpu_SetBASEPRI (component MK70FN1M0MJ15)
+**
+** Description :
+** This method sets the BASEPRI core register.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+/*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */
+#ifdef _lint
+ #define Cpu_SetBASEPRI(Level) /* empty */
+#else
+void Cpu_SetBASEPRI(uint32_t Level) {
+ __asm ("msr basepri, %[input]"::[input] "r" (Level):);
+}
+#endif
+/*lint -restore Enable MISRA rule (2.1,1.1) checking. */
+
+
+/*
+** ===================================================================
+** Method : PE_low_level_init (component MK70FN1M0MJ15)
+**
+** Description :
+** Initializes beans and provides common register initialization.
+** The method is called automatically as a part of the
+** application initialization code.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+void PE_low_level_init(void)
+{
+ #ifdef PEX_RTOS_INIT
+ PEX_RTOS_INIT(); /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
+ #endif
+ /* Initialization of the SIM module */
+ /* SIM_SOPT2: CMTUARTPAD=0 */
+ SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_CMTUARTPAD_MASK);
+ /* PORTA_PCR4: MUX=0 */
+ PORTA_PCR4 &= (uint32_t)~(uint32_t)(PORT_PCR_MUX(0x07)); /* Disable NMI function on the NMI pin */
+ /* Initialization of the RCM module */
+ /* RCM_RPFW: RSTFLTSEL=0 */
+ RCM_RPFW &= (uint8_t)~(uint8_t)(RCM_RPFW_RSTFLTSEL(0x1F));
+ /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */
+ RCM_RPFC &= (uint8_t)~(uint8_t)(
+ RCM_RPFC_RSTFLTSS_MASK |
+ RCM_RPFC_RSTFLTSRW(0x03)
+ );
+ /* Initialization of the FTFL_FlashConfig module */
+ /* SIM_SCGC7: MPU=1 */
+ SIM_SCGC7 |= SIM_SCGC7_MPU_MASK;
+ /* Initialization of the MPU module */
+ /* MPU_CESR: SPERR=0,VLD=0 */
+ MPU_CESR &= (uint32_t)~(uint32_t)((MPU_CESR_SPERR(0xFF) | MPU_CESR_VLD_MASK));
+ /* Initialization of the PMC module */
+ /* PMC_REGSC: ACKISO=0,BGBE=0 */
+ PMC_REGSC &= (uint8_t)~(uint8_t)(
+ PMC_REGSC_ACKISO_MASK |
+ PMC_REGSC_BGBE_MASK
+ );
+ /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
+ PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)(
+ PMC_LVDSC1_LVDIE_MASK |
+ PMC_LVDSC1_LVDV(0x03)
+ )) | (uint8_t)(
+ PMC_LVDSC1_LVDACK_MASK |
+ PMC_LVDSC1_LVDRE_MASK
+ ));
+ /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
+ PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)(
+ PMC_LVDSC2_LVWIE_MASK |
+ PMC_LVDSC2_LVWV(0x03)
+ )) | (uint8_t)(
+ PMC_LVDSC2_LVWACK_MASK
+ ));
+ /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
+ SMC_PMPROT = 0x00U; /* Setup Power mode protection register */
+ /* Common initialization of the CPU registers */
+ /* NVICIP20: PRI20=0 */
+ NVICIP20 = NVIC_IP_PRI20(0x00);
+ /* Enable interrupts of the given priority level */
+ Cpu_SetBASEPRI(0U);
+}
+ /* Flash configuration field */
+ __attribute__ ((section (".cfmconfig"))) const uint8_t _cfm[0x10] = {
+ /* NV_BACKKEY3: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY2: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY1: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY0: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY7: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY6: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY5: KEY=0xFF */
+ 0xFFU,
+ /* NV_BACKKEY4: KEY=0xFF */
+ 0xFFU,
+ /* NV_FPROT3: PROT=0xFF */
+ 0xFFU,
+ /* NV_FPROT2: PROT=0xFF */
+ 0xFFU,
+ /* NV_FPROT1: PROT=0xFF */
+ 0xFFU,
+ /* NV_FPROT0: PROT=0xFF */
+ 0xFFU,
+ /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0x7EU,
+ /* NV_FOPT: ??=1,??=1,??=1,??=1,??=1,??=1,EZPORT_DIS=1,LPBOOT=1 */
+ 0xFFU,
+ /* NV_FEPROT: EPROT=0xFF */
+ 0xFFU,
+ /* NV_FDPROT: DPROT=0xFF */
+ 0xFFU
+ };
+
+/* END Cpu. */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/Cpu.h b/Generated_Code/Cpu.h
new file mode 100644
index 0000000000000000000000000000000000000000..5494a7ad4c9b3b077ee27b61f0889035a0d8a283
--- /dev/null
+++ b/Generated_Code/Cpu.h
@@ -0,0 +1,202 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : Cpu.h
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : MK70FN1M0MJ15
+** Version : Component 01.028, Driver 01.04, CPU db: 3.00.000
+** Repository : Kinetis
+** Datasheet : K70P256M150SF3RM, Rev. 2, Dec 2011
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+**
+** Settings :
+**
+** Contents :
+** No public methods
+**
+** (c) Freescale Semiconductor, Inc.
+** 2004 All Rights Reserved
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file Cpu.h
+** @version 01.04
+** @brief
+**
+*/
+/*!
+** @addtogroup Cpu_module Cpu module documentation
+** @{
+*/
+
+#ifndef __Cpu_H
+#define __Cpu_H
+
+/* MODULE Cpu. */
+/*Include shared modules, which are used for whole project*/
+#include "PE_Types.h"
+#include "PE_Error.h"
+#include "PE_Const.h"
+#include "IO_Map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Active configuration define symbol */
+#define PEcfg_FLASH 1U
+
+/* Methods configuration constants - generated for all enabled component's methods */
+
+/* Events configuration constants - generated for all enabled component's events */
+
+#define CPU_BUS_CLK_HZ 20971520U /* Initial value of the bus clock frequency in Hz */
+#define CPU_CORE_CLK_HZ 20971520U /* Initial value of the core/system clock frequency in Hz. */
+
+#define CPU_CLOCK_CONFIG_NUMBER 0x01U /* Specifies number of defined clock configurations. */
+
+#define CPU_BUS_CLK_HZ_CLOCK_CONFIG0 20971520U /* Value of the bus clock frequency in the clock configuration 0 in Hz. */
+#define CPU_CORE_CLK_HZ_CLOCK_CONFIG0 20971520U /* Value of the core/system clock frequency in the clock configuration 0 in Hz. */
+
+
+#define CPU_INT_SLOW_CLK_HZ 32768U /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000U /* Value of the fast internal oscillator clock frequency in Hz */
+
+#define CPU_FAMILY_Kinetis /* Specification of the core type of the selected cpu */
+#define CPU_DERIVATIVE_MK70FN1M0MJ15 /* Name of the selected cpu derivative */
+#define CPU_PARTNUM_MK70FN1M0VMJ12 /* Part number of the selected cpu */
+#define CPU_LITTLE_ENDIAN /* The selected cpu uses little endian */
+
+/* CPU frequencies in clock configuration 0 */
+#define CPU_CLOCK_CONFIG_0 0x00U /* Clock configuration 0 identifier */
+#define CPU_CORE_CLK_HZ_CONFIG_0 20971520UL /* Core clock frequency in clock configuration 0 */
+#define CPU_BUS_CLK_HZ_CONFIG_0 20971520UL /* Bus clock frequency in clock configuration 0 */
+#define CPU_FLEXBUS_CLK_HZ_CONFIG_0 10485760UL /* Flexbus clock frequency in clock configuration 0 */
+#define CPU_FLASH_CLK_HZ_CONFIG_0 10485760UL /* FLASH clock frequency in clock configuration 0 */
+#define CPU_USB_CLK_HZ_CONFIG_0 0UL /* USB clock frequency in clock configuration 0 */
+#define CPU_PLL_FLL_CLK_HZ_CONFIG_0 20971520UL /* PLL/FLL clock frequency in clock configuration 0 */
+#define CPU_MCGIR_CLK_HZ_CONFIG_0 32768UL /* MCG internal reference clock frequency in clock configuration 0 */
+#define CPU_OSCER_CLK_HZ_CONFIG_0 0UL /* System OSC external reference clock frequency in clock configuration 0 */
+#define CPU_ERCLK32K_CLK_HZ_CONFIG_0 0UL /* External reference clock 32k frequency in clock configuration 0 */
+#define CPU_MCGFF_CLK_HZ_CONFIG_0 16384UL /* MCG fixed frequency clock */
+
+
+typedef struct {
+ uint32_t cpu_core_clk_hz; /* Core clock frequency in clock configuration */
+ uint32_t cpu_bus_clk_hz; /* Bus clock frequency in clock configuration */
+ uint32_t cpu_flexbus_clk_hz; /* Flexbus clock frequency in clock configuration */
+ uint32_t cpu_flash_clk_hz; /* FLASH clock frequency in clock configuration */
+ uint32_t cpu_usb_clk_hz; /* USB clock frequency in clock configuration */
+ uint32_t cpu_pll_fll_clk_hz; /* PLL/FLL clock frequency in clock configuration */
+ uint32_t cpu_mcgir_clk_hz; /* MCG internal reference clock frequency in clock configuration */
+ uint32_t cpu_oscer_clk_hz; /* System OSC external reference clock frequency in clock configuration */
+ uint32_t cpu_erclk32k_clk_hz; /* External reference clock 32k frequency in clock configuration */
+ uint32_t cpu_mcgff_clk_hz; /* MCG fixed frequency clock */
+} TCpuClockConfiguration;
+
+/* The array of clock frequencies in configured clock configurations */
+extern const TCpuClockConfiguration PE_CpuClockConfigurations[CPU_CLOCK_CONFIG_NUMBER];
+
+ /* Interrupt vector table type definition */
+ typedef void (*const tIsrFunc)(void);
+ typedef struct {
+ void * __ptr;
+ tIsrFunc __fun[0x79];
+ } tVectorTable;
+
+ extern const tVectorTable __vect_table;
+
+/* Global variables */
+/*lint -esym(765,SR_reg) Disable MISRA rule (8.10) checking for symbols (SR_reg). The SR_reg is used in inline assembler. */
+extern volatile uint8_t SR_reg; /* Current FAULTMASK register */
+/*lint -esym(765,SR_lock) Disable MISRA rule (8.10) checking for symbols (SR_lock). The SR_reg is used in inline assembler. */
+extern volatile uint8_t SR_lock;
+
+
+/*
+** ===================================================================
+** Method : PE_low_level_init (component MK70FN1M0MJ15)
+**
+** Description :
+** Initializes beans and provides common register initialization.
+** The method is called automatically as a part of the
+** application initialization code.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+void PE_low_level_init(void);
+
+PE_ISR(Cpu_Interrupt);
+/*
+** ===================================================================
+** Method : Cpu_Cpu_Interrupt (component MK70FN1M0MJ15)
+**
+** Description :
+** This ISR services an unused interrupt/exception vector.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+
+void __init_hardware(void);
+/*
+** ===================================================================
+** Method : __init_hardware (component MK70FN1M0MJ15)
+**
+** Description :
+** Initializes the whole system like timing, external bus, etc.
+** This method is internal. It is used by Processor Expert only.
+** ===================================================================
+*/
+
+/* END Cpu. */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif
+/* __Cpu_H */
+
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/IO_Map.h b/Generated_Code/IO_Map.h
new file mode 100644
index 0000000000000000000000000000000000000000..e0a531c7c8fc69fef6bd3e407bf63f594ef0427d
--- /dev/null
+++ b/Generated_Code/IO_Map.h
@@ -0,0 +1,79 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : IO_Map.h
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : IO_Map
+** Version : Driver 01.00
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+** IO_Map.h - implements an IO device's mapping.
+** This module contains symbol definitions of all peripheral
+** registers and bits.
+** Contents :
+** No public methods
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file IO_Map.h
+** @version 01.00
+** @brief
+** IO_Map.h - implements an IO device's mapping.
+** This module contains symbol definitions of all peripheral
+** registers and bits.
+*/
+/*!
+** @addtogroup IO_Map_module IO_Map module documentation
+** @{
+*/
+
+#ifndef __IO_Map_H
+#define __IO_Map_H
+
+#include "MK70F12.h"
+
+#endif
+/* __IO_Map_H */
+
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/PE_Const.h b/Generated_Code/PE_Const.h
new file mode 100644
index 0000000000000000000000000000000000000000..0ad9341d8c32e6eac3e24236acf0dc35d6baf645
--- /dev/null
+++ b/Generated_Code/PE_Const.h
@@ -0,0 +1,94 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : PE_Const.h
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : PE_Const
+** Version : Driver 01.00
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+** This component "PE_Const" contains internal definitions
+** of the constants.
+** Contents :
+** No public methods
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file PE_Const.h
+** @version 01.00
+** @brief
+** This component "PE_Const" contains internal definitions
+** of the constants.
+*/
+/*!
+** @addtogroup PE_Const_module PE_Const module documentation
+** @{
+*/
+
+#ifndef __PE_Const_H
+#define __PE_Const_H
+
+
+/* Reset cause constants */
+#define RSTSRC_WAKEUP 0x01U /*!< LLWU module wakeup reset */
+#define RSTSRC_LVD 0x02U /*!< Low-voltage detect reset */
+#define RSTSRC_LOC 0x04U /*!< Loss-of-clock reset */
+#define RSTSRC_COP 0x20U /*!< Watchdog reset */
+#define RSTSRC_WDOG 0x20U /*!< Watchdog reset */
+#define RSTSRC_PIN 0x40U /*!< External pin reset */
+#define RSTSRC_POR 0x80U /*!< Power-on reset */
+#define RSTSRC_JTAG 0x0100U /*!< JTAG reset pin */
+#define RSTSRC_LOCKUP 0x0200U /*!< Core Lock-up reset */
+#define RSTSRC_SW 0x0400U /*!< Software reset */
+#define RSTSRC_MDM_AP 0x0800U /*!< Reset caused by host debugger system */
+#define RSTSRC_EZPT 0x1000U /*!< EzPort reset */
+#define RSTSRC_SACKERR 0x2000U /*!< Stop Mode Acknowledge Error Reset */
+
+
+/* Low voltage interrupt cause constants */
+#define LVDSRC_LVD 0x01U /*!< Low voltage detect */
+#define LVDSRC_LVW 0x02U /*!< Low-voltage warning */
+
+#endif /* _PE_Const_H */
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/PE_Error.h b/Generated_Code/PE_Error.h
new file mode 100644
index 0000000000000000000000000000000000000000..810fc110065e88cde38a7f1a785ba437e45e96d3
--- /dev/null
+++ b/Generated_Code/PE_Error.h
@@ -0,0 +1,128 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : PE_Error.h
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : PE_Error
+** Version : Driver 01.00
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+** This component "PE_Error" contains internal definitions
+** of the error constants.
+** Contents :
+** No public methods
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file PE_Error.h
+** @version 01.00
+** @brief
+** This component "PE_Error" contains internal definitions
+** of the error constants.
+*/
+/*!
+** @addtogroup PE_Error_module PE_Error module documentation
+** @{
+*/
+
+#ifndef __PE_Error_H
+#define __PE_Error_H
+
+#define ERR_OK 0x00U /*!< OK */
+#define ERR_SPEED 0x01U /*!< This device does not work in the active speed mode. */
+#define ERR_RANGE 0x02U /*!< Parameter out of range. */
+#define ERR_VALUE 0x03U /*!< Parameter of incorrect value. */
+#define ERR_OVERFLOW 0x04U /*!< Timer overflow. */
+#define ERR_MATH 0x05U /*!< Overflow during evaluation. */
+#define ERR_ENABLED 0x06U /*!< Device is enabled. */
+#define ERR_DISABLED 0x07U /*!< Device is disabled. */
+#define ERR_BUSY 0x08U /*!< Device is busy. */
+#define ERR_NOTAVAIL 0x09U /*!< Requested value or method not available. */
+#define ERR_RXEMPTY 0x0AU /*!< No data in receiver. */
+#define ERR_TXFULL 0x0BU /*!< Transmitter is full. */
+#define ERR_BUSOFF 0x0CU /*!< Bus not available. */
+#define ERR_OVERRUN 0x0DU /*!< Overrun error is detected. */
+#define ERR_FRAMING 0x0EU /*!< Framing error is detected. */
+#define ERR_PARITY 0x0FU /*!< Parity error is detected. */
+#define ERR_NOISE 0x10U /*!< Noise error is detected. */
+#define ERR_IDLE 0x11U /*!< Idle error is detected. */
+#define ERR_FAULT 0x12U /*!< Fault error is detected. */
+#define ERR_BREAK 0x13U /*!< Break char is received during communication. */
+#define ERR_CRC 0x14U /*!< CRC error is detected. */
+#define ERR_ARBITR 0x15U /*!< A node losts arbitration. This error occurs if two nodes start transmission at the same time. */
+#define ERR_PROTECT 0x16U /*!< Protection error is detected. */
+#define ERR_UNDERFLOW 0x17U /*!< Underflow error is detected. */
+#define ERR_UNDERRUN 0x18U /*!< Underrun error is detected. */
+#define ERR_COMMON 0x19U /*!< Common error of a device. */
+#define ERR_LINSYNC 0x1AU /*!< LIN synchronization error is detected. */
+#define ERR_FAILED 0x1BU /*!< Requested functionality or process failed. */
+#define ERR_QFULL 0x1CU /*!< Queue is full. */
+#define ERR_PARAM_MASK 0x80U /*!< Invalid mask. */
+#define ERR_PARAM_MODE 0x81U /*!< Invalid mode. */
+#define ERR_PARAM_INDEX 0x82U /*!< Invalid index. */
+#define ERR_PARAM_DATA 0x83U /*!< Invalid data. */
+#define ERR_PARAM_SIZE 0x84U /*!< Invalid size. */
+#define ERR_PARAM_VALUE 0x85U /*!< Invalid value. */
+#define ERR_PARAM_RANGE 0x86U /*!< Invalid parameter's range or parameters' combination. */
+#define ERR_PARAM_LOW_VALUE 0x87U /*!< Invalid value (LOW part). */
+#define ERR_PARAM_HIGH_VALUE 0x88U /*!< Invalid value (HIGH part). */
+#define ERR_PARAM_ADDRESS 0x89U /*!< Invalid address. */
+#define ERR_PARAM_PARITY 0x8AU /*!< Invalid parity. */
+#define ERR_PARAM_WIDTH 0x8BU /*!< Invalid width. */
+#define ERR_PARAM_LENGTH 0x8CU /*!< Invalid length. */
+#define ERR_PARAM_ADDRESS_TYPE 0x8DU /*!< Invalid address type. */
+#define ERR_PARAM_COMMAND_TYPE 0x8EU /*!< Invalid command type. */
+#define ERR_PARAM_COMMAND 0x8FU /*!< Invalid command. */
+#define ERR_PARAM_RECIPIENT 0x90U /*!< Invalid recipient. */
+#define ERR_PARAM_BUFFER_COUNT 0x91U /*!< Invalid buffer count. */
+#define ERR_PARAM_ID 0x92U /*!< Invalid ID. */
+#define ERR_PARAM_GROUP 0x93U /*!< Invalid group. */
+#define ERR_PARAM_CHIP_SELECT 0x94U /*!< Invalid chip select. */
+#define ERR_PARAM_ATTRIBUTE_SET 0x95U /*!< Invalid set of attributes. */
+#define ERR_PARAM_SAMPLE_COUNT 0x96U /*!< Invalid sample count. */
+#define ERR_PARAM_CONDITION 0x97U /*!< Invalid condition. */
+#define ERR_PARAM_TICKS 0x98U /*!< Invalid ticks parameter. */
+
+#endif /* __PE_Error_H */
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/PE_Types.h b/Generated_Code/PE_Types.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d175f45f7c061e5e81ce9510d1ccffb00f7c387
--- /dev/null
+++ b/Generated_Code/PE_Types.h
@@ -0,0 +1,2587 @@
+/* ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : PE_Types.h
+** Project : Lab0
+** Processor : MK70FN1M0VMJ12
+** Component : PE_Types
+** Version : Driver 01.01
+** Compiler : GNU C Compiler
+** Date/Time : 2018-07-15, 23:43, # CodeGen: 0
+** Abstract :
+** PE_Types.h - contains definitions of basic types,
+** register access macros and hardware specific macros
+** which can be used in user application.
+** Contents :
+** No public methods
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file PE_Types.h
+** @version 01.01
+** @brief
+** PE_Types.h - contains definitions of basic types,
+** register access macros and hardware specific macros
+** which can be used in user application.
+*/
+/*!
+** @addtogroup PE_Types_module PE_Types module documentation
+** @{
+*/
+
+#ifndef __PE_Types_H
+#define __PE_Types_H
+
+/* Standard ANSI C types */
+#include
+
+#ifndef FALSE
+ #define FALSE 0x00u /* Boolean value FALSE. FALSE is defined always as a zero value. */
+#endif
+#ifndef TRUE
+ #define TRUE 0x01u /* Boolean value TRUE. TRUE is defined always as a non zero value. */
+#endif
+
+#ifndef NULL
+ #define NULL 0x00u
+#endif
+
+/* PE types definition */
+#ifndef __cplusplus
+ #ifndef bool
+typedef unsigned char bool;
+ #endif
+#endif
+typedef unsigned char byte;
+typedef unsigned short word;
+typedef unsigned long dword;
+typedef unsigned long long dlong;
+typedef unsigned char TPE_ErrCode;
+#ifndef TPE_Float
+typedef float TPE_Float;
+#endif
+#ifndef char_t
+typedef char char_t;
+#endif
+
+/* Other basic data types */
+typedef signed char int8;
+typedef signed short int int16;
+typedef signed long int int32;
+
+typedef unsigned char uint8;
+typedef unsigned short int uint16;
+typedef unsigned long int uint32;
+
+
+/**********************************************************/
+/* Uniform multiplatform 8-bits peripheral access macros */
+/**********************************************************/
+
+/* Enable maskable interrupts */
+#define __EI()\
+ do {\
+ /*lint -save -e950 Disable MISRA rule (1.1) checking. */\
+ __asm("CPSIE f");\
+ /*lint -restore Enable MISRA rule (1.1) checking. */\
+ } while(0)
+
+/* Disable maskable interrupts */
+#define __DI() \
+ do {\
+ /*lint -save -e950 Disable MISRA rule (1.1) checking. */\
+ __asm ("CPSID f");\
+ /*lint -restore Enable MISRA rule (1.1) checking. */\
+ } while(0)
+
+
+
+/* Save status register and disable interrupts */
+#define EnterCritical() \
+ do {\
+ uint8_t SR_reg_local;\
+ /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\
+ __asm ( \
+ "MRS R0, FAULTMASK\n\t" \
+ "CPSID f\n\t" \
+ "STRB R0, %[output]" \
+ : [output] "=m" (SR_reg_local)\
+ :: "r0");\
+ /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\
+ if (++SR_lock == 1u) {\
+ SR_reg = SR_reg_local;\
+ }\
+ } while(0)
+
+
+/* Restore status register */
+#define ExitCritical() \
+ do {\
+ if (--SR_lock == 0u) { \
+ /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\
+ __asm ( \
+ "ldrb r0, %[input]\n\t"\
+ "msr FAULTMASK,r0;\n\t" \
+ ::[input] "m" (SR_reg) \
+ : "r0"); \
+ /*lint -restore Enable MISRA rule (2.1,1.1) checking. */\
+ }\
+ } while(0)
+
+
+#define PE_DEBUGHALT() \
+ /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\
+ __asm( "BKPT 255") \
+ /*lint -restore Enable MISRA rule (2.1,1.1) checking. */
+
+#define PE_NOP() \
+ /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\
+ __asm( "NOP") \
+ /*lint -restore Enable MISRA rule (2.1,1.1) checking. */
+
+#define PE_WFI() \
+ /*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */\
+ __asm("WFI") \
+ /*lint -restore Enable MISRA rule (2.1,1.1) checking. */
+
+
+/* Interrupt definition template */
+#if !defined(PE_ISR)
+ #define PE_ISR(ISR_name) void __attribute__ ((interrupt)) ISR_name(void)
+#endif
+
+/* Logical Device Drivers (LDD) types */
+
+/*! Logical Device Driver API version */
+#define PE_LDD_VERSION 0x0100U
+
+/* LDD driver states */
+#define PE_LDD_DRIVER_DISABLED_IN_CLOCK_CONFIGURATION 0x01U /*!< LDD driver is disabled in the selected clock configuration */
+#define PE_LDD_DRIVER_DISABLED_BY_USER 0x02U /*!< LDD driver is disabled by the user */
+#define PE_LDD_DRIVER_BUSY 0x04U /*!< LDD driver is busy */
+
+/*! Macro to register component device structure */
+#define PE_LDD_RegisterDeviceStructure(ComponentIndex, DeviceStructure) (PE_LDD_DeviceDataList[ComponentIndex] = DeviceStructure)
+
+/*! Macro to unregister component device structure */
+#define PE_LDD_UnregisterDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex] = NULL)
+
+/*! Macro to get the component device structure */
+#define PE_LDD_GetDeviceStructure(ComponentIndex) (PE_LDD_DeviceDataList[ComponentIndex])
+
+/*
+** ===================================================================
+** Global HAL types and constants
+** ===================================================================
+*/
+typedef uint32_t LDD_TPinMask; /*!< Pin mask type. */
+typedef uint16_t LDD_TError; /*!< Error type. */
+typedef uint32_t LDD_TEventMask; /*!< Event mask type. */
+typedef uint8_t LDD_TClockConfiguration; /*!< CPU clock configuration type. */
+typedef void LDD_TDeviceData; /*!< Pointer to private device structure managed and used by HAL components. */
+typedef void* LDD_TDeviceDataPtr; /*!< Obsolete type for backward compatibility. */
+typedef void LDD_TData; /*!< General pointer to data. */
+typedef void LDD_TUserData; /*!< Pointer to this type specifies the user or RTOS specific data will be passed as an event or callback parameter. */
+
+/*! Driver operation mode type. */
+typedef enum {
+ DOM_NONE,
+ DOM_RUN,
+ DOM_WAIT,
+ DOM_SLEEP,
+ DOM_STOP
+} LDD_TDriverOperationMode;
+
+typedef uint16_t LDD_TDriverState; /*!< Driver state type. */
+typedef void LDD_TCallbackParam; /*!< Pointer to this type specifies the user data to be passed as a callback parameter. */
+typedef void (* LDD_TCallback)(LDD_TCallbackParam *CallbackParam); /*!< Callback type used for definition of callback functions. */
+
+
+/* Fills a memory area block by a specified value. Function defined in PE_LDD.c */
+extern void PE_FillMemory(register void* SourceAddressPtr, register uint8_t c, register uint32_t len);
+
+
+/*
+** ===================================================================
+** RTOS specific types and constants
+** ===================================================================
+*/
+/* {Default RTOS Adapter} RTOS specific definition of type of Ioctl() command constants */
+
+
+/*
+** ===================================================================
+** Published RTOS settings and constants
+** ===================================================================
+*/
+/* {Default RTOS Adapter} No published RTOS settings */
+
+
+/*
+** ===================================================================
+** TimerUnit device types and constants
+** ===================================================================
+*/
+#define LDD_TIMERUNIT_ON_CHANNEL_0 0x01u /*!< OnChannel0 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_1 0x02u /*!< OnChannel1 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_2 0x04u /*!< OnChannel2 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_3 0x08u /*!< OnChannel3 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_4 0x10u /*!< OnChannel4 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_5 0x20u /*!< OnChannel5 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_6 0x40u /*!< OnChannel6 event mask value */
+#define LDD_TIMERUNIT_ON_CHANNEL_7 0x80u /*!< OnChannel7 event mask value */
+#define LDD_TIMERUNIT_ON_COUNTER_RESTART 0x0100u /*!< OnCounterRestart event mask value */
+
+/*! Direction of counting */
+typedef enum {
+ DIR_UP, /*!< UP */
+ DIR_DOWN /*!< DOWN */
+} LDD_TimerUnit_TCounterDirection;
+
+/*! Output action type (flip-flop action on overrun or compare match) */
+typedef enum {
+ OUTPUT_NONE, /*!< NONE */
+ OUTPUT_TOGGLE, /*!< TOGGLE */
+ OUTPUT_CLEAR, /*!< CLEAR */
+ OUTPUT_SET /*!< SET */
+} LDD_TimerUnit_TOutAction;
+
+/*! Input edge type */
+typedef enum {
+ EDGE_NONE, /*!< NONE */
+ EDGE_RISING, /*!< RISING */
+ EDGE_FALLING, /*!< FALLING */
+ EDGE_BOTH /*!< BOTH */
+} LDD_TimerUnit_TEdge;
+
+typedef float LDD_TimerUnit_Tfloat; /*!< Float type */
+
+/*
+** ===================================================================
+** CMT device types and constants
+** ===================================================================
+*/
+#define LDD_CMT_ON_END 0x01u /*!< OnEnd event mask value */
+
+/*
+** ===================================================================
+** PPG device types and constants
+** ===================================================================
+*/
+#define LDD_PPG_ON_END 0x01u /*!< OnEnd event mask value */
+
+typedef float LDD_PPG_Tfloat; /*!< Float type */
+
+/*
+** ===================================================================
+** PWM types and constants
+** ===================================================================
+*/
+#define LDD_PWM_ON_END 0x01u /*!< OnEnd event mask value */
+
+/*
+** ===================================================================
+** Capture types and constants
+** ===================================================================
+*/
+#define LDD_CAPTURE_ON_CAPTURE 0x01u /*!< OnCapture event mask value */
+#define LDD_CAPTURE_ON_OVERRUN 0x02u /*!< OnOverrun event mask value */
+
+/*
+** ===================================================================
+** TimerInt types and constants
+** ===================================================================
+*/
+#define LDD_TIMERINT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */
+
+/*
+** ===================================================================
+** TimerOut types and constants
+** ===================================================================
+*/
+#define LDD_TIMEROUT_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */
+
+/*
+** ===================================================================
+** EventCntr types and constants
+** ===================================================================
+*/
+#define LDD_EVENTCNTR_ON_END 0x01u /*!< OnEnd event mask value */
+
+/*
+** ===================================================================
+** FreeCntr types and constants
+** ===================================================================
+*/
+#define LDD_FREECNTR_ON_INTERRUPT 0x01u /*!< OnInterrupt event mask value */
+
+/*
+** ===================================================================
+** RealTime types and constants
+** ===================================================================
+*/
+
+typedef float LDD_RealTime_Tfloat; /*!< Float type */
+
+/*
+** ===================================================================
+** TimeDate types and constants
+** ===================================================================
+*/
+#define LDD_TIMEDATE_ON_ALARM 0x01u /*!< OnAlarm event mask value */
+#define LDD_TIMEDATE_ON_SECOND 0x02u /*!< OnSecond event mask value */
+
+/*!< Time struct */
+typedef struct {
+ uint16_t Hour; /*!< Hours (0 - 23) */
+ uint16_t Min; /*!< Minutes (0 - 59) */
+ uint16_t Sec; /*!< Seconds (0 - 59) */
+ uint16_t Sec100; /*!< Hundredths of seconds (0 - 99) */
+} LDD_TimeDate_TTimeRec;
+
+/*!< Date struct */
+typedef struct {
+ uint16_t Year; /*!< Years (1998 - 2099) */
+ uint16_t Month; /*!< Months (1 - 12) */
+ uint16_t Day; /*!< Days (1 - 31) */
+ uint16_t DayOfWeek; /*!< Day of week (0-Sunday, .. 6-Saturday) */
+} LDD_TimeDate_TDateRec;
+
+/*
+** ===================================================================
+** UART device types and constants
+** ===================================================================
+*/
+#define LDD_SERIAL_RX_PIN 0x01u /*!< Receiver pin mask */
+#define LDD_SERIAL_TX_PIN 0x02u /*!< Transmitter pin mask */
+#define LDD_SERIAL_CTS_PIN 0x04u /*!< CTS pin mask */
+#define LDD_SERIAL_RTS_PIN 0x08u /*!< RTS pin mask */
+
+#define LDD_SERIAL_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */
+#define LDD_SERIAL_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */
+#define LDD_SERIAL_ON_BREAK 0x04u /*!< OnBreak event mask */
+#define LDD_SERIAL_ON_TXCOMPLETE 0x08u /*!< OnTxComplete event mask */
+#define LDD_SERIAL_ON_ERROR 0x10u /*!< OnError event mask */
+
+#define LDD_SERIAL_RX_OVERRUN 0x01u /*!< Receiver overrun */
+#define LDD_SERIAL_PARITY_ERROR 0x02u /*!< Parity error */
+#define LDD_SERIAL_FRAMING_ERROR 0x04u /*!< Framing error */
+#define LDD_SERIAL_NOISE_ERROR 0x08u /*!< Noise error */
+
+typedef uint32_t LDD_SERIAL_TError; /*!< Serial communication error type */
+
+typedef uint8_t LDD_SERIAL_TDataWidth; /*!< Bit length type. The number of bits transmitted by one character. */
+
+typedef uint16_t LDD_SERIAL_TSize; /*!< Type specifying the length of the data or buffer. */
+
+typedef uint8_t LDD_SERIAL_TBaudMode; /*!< Type specifying the baud mode. */
+
+/*! Type specifying the parity. */
+typedef enum {
+ LDD_SERIAL_PARITY_UNDEF, /*!< Undefined parity */
+ LDD_SERIAL_PARITY_NONE, /*!< Parity none */
+ LDD_SERIAL_PARITY_ODD, /*!< Parity odd */
+ LDD_SERIAL_PARITY_EVEN, /*!< Parity even */
+ LDD_SERIAL_PARITY_MARK, /*!< Parity mark */
+ LDD_SERIAL_PARITY_SPACE /*!< Parity space */
+} LDD_SERIAL_TParity;
+
+/*! Type specifying the stop bit length. */
+typedef enum {
+ LDD_SERIAL_STOP_BIT_LEN_UNDEF, /*!< Undefined bit length */
+ LDD_SERIAL_STOP_BIT_LEN_1, /*!< 1 bit length */
+ LDD_SERIAL_STOP_BIT_LEN_1_5, /*!< 1.5 bit length */
+ LDD_SERIAL_STOP_BIT_LEN_2 /*!< 2 bit length */
+} LDD_SERIAL_TStopBitLen;
+
+/*! Communication statistics */
+typedef struct {
+ uint32_t ReceivedChars; /*!< Number of received characters */
+ uint32_t SentChars; /*!< Number of transmitted characters */
+ uint32_t ReceivedBreaks; /*!< Number of received break characters */
+ uint32_t ParityErrors; /*!< Number of receiver parity errors */
+ uint32_t FramingErrors; /*!< Number of receiver framing errors */
+ uint32_t OverrunErrors; /*!< Number of receiver overrun errors */
+ uint32_t NoiseErrors; /*!< Number of receiver noise errors */
+} LDD_SERIAL_TStats;
+
+/*! Type specifying the loop mode operation. */
+typedef enum {
+ LOOPMODE_UNDEF, /*!< Undefined loop mode */
+ LOOPMODE_NORMAL, /*!< Normal operation */
+ LOOPMODE_AUTO_ECHO, /*!< Auto echo mode */
+ LOOPMODE_LOCAL_LOOPBACK, /*!< Local loopback mode */
+ LOOPMODE_REMOTE_LOOPBACK /*!< Remote loopback mode */
+} LDD_SERIAL_TLoopMode;
+
+
+/*
+** ===================================================================
+** ADC device types and constants
+** ===================================================================
+*/
+
+#define LDD_ADC_CHANNEL_0_PIN 0x01u /*!< Channel 0 pin mask */
+#define LDD_ADC_CHANNEL_1_PIN 0x02u /*!< Channel 1 pin mask */
+#define LDD_ADC_CHANNEL_2_PIN 0x04u /*!< Channel 2 pin mask */
+#define LDD_ADC_CHANNEL_3_PIN 0x08u /*!< Channel 3 pin mask */
+#define LDD_ADC_CHANNEL_4_PIN 0x10u /*!< Channel 4 pin mask */
+#define LDD_ADC_CHANNEL_5_PIN 0x20u /*!< Channel 5 pin mask */
+#define LDD_ADC_CHANNEL_6_PIN 0x40u /*!< Channel 6 pin mask */
+#define LDD_ADC_CHANNEL_7_PIN 0x80u /*!< Channel 7 pin mask */
+#define LDD_ADC_CHANNEL_8_PIN 0x0100u /*!< Channel 8 pin mask */
+#define LDD_ADC_CHANNEL_9_PIN 0x0200u /*!< Channel 9 pin mask */
+#define LDD_ADC_CHANNEL_10_PIN 0x0400u /*!< Channel 10 pin mask */
+#define LDD_ADC_CHANNEL_11_PIN 0x0800u /*!< Channel 11 pin mask */
+#define LDD_ADC_CHANNEL_12_PIN 0x1000u /*!< Channel 12 pin mask */
+#define LDD_ADC_CHANNEL_13_PIN 0x2000u /*!< Channel 13 pin mask */
+#define LDD_ADC_CHANNEL_14_PIN 0x4000u /*!< Channel 14 pin mask */
+#define LDD_ADC_CHANNEL_15_PIN 0x8000u /*!< Channel 15 pin mask */
+#define LDD_ADC_CHANNEL_16_PIN 0x00010000u /*!< Channel 16 pin mask */
+#define LDD_ADC_CHANNEL_17_PIN 0x00020000u /*!< Channel 17 pin mask */
+#define LDD_ADC_CHANNEL_18_PIN 0x00040000u /*!< Channel 18 pin mask */
+#define LDD_ADC_CHANNEL_19_PIN 0x00080000u /*!< Channel 19 pin mask */
+#define LDD_ADC_CHANNEL_20_PIN 0x00100000u /*!< Channel 20 pin mask */
+#define LDD_ADC_CHANNEL_21_PIN 0x00200000u /*!< Channel 21 pin mask */
+#define LDD_ADC_CHANNEL_22_PIN 0x00400000u /*!< Channel 22 pin mask */
+#define LDD_ADC_CHANNEL_23_PIN 0x00800000u /*!< Channel 23 pin mask */
+#define LDD_ADC_CHANNEL_24_PIN 0x01000000u /*!< Channel 24 pin mask */
+#define LDD_ADC_CHANNEL_25_PIN 0x02000000u /*!< Channel 25 pin mask */
+#define LDD_ADC_CHANNEL_26_PIN 0x04000000u /*!< Channel 26 pin mask */
+#define LDD_ADC_CHANNEL_27_PIN 0x08000000u /*!< Channel 27 pin mask */
+#define LDD_ADC_CHANNEL_28_PIN 0x10000000u /*!< Channel 28 pin mask */
+#define LDD_ADC_CHANNEL_29_PIN 0x20000000u /*!< Channel 29 pin mask */
+#define LDD_ADC_CHANNEL_30_PIN 0x40000000u /*!< Channel 30 pin mask */
+#define LDD_ADC_CHANNEL_31_PIN 0x80000000u /*!< Channel 31 pin mask */
+#define LDD_ADC_CHANNEL_32_PIN 0x01u /*!< Channel 32 pin mask */
+#define LDD_ADC_CHANNEL_33_PIN 0x02u /*!< Channel 33 pin mask */
+#define LDD_ADC_CHANNEL_34_PIN 0x04u /*!< Channel 34 pin mask */
+#define LDD_ADC_CHANNEL_35_PIN 0x08u /*!< Channel 35 pin mask */
+#define LDD_ADC_CHANNEL_36_PIN 0x10u /*!< Channel 36 pin mask */
+#define LDD_ADC_CHANNEL_37_PIN 0x20u /*!< Channel 37 pin mask */
+#define LDD_ADC_CHANNEL_38_PIN 0x40u /*!< Channel 38 pin mask */
+#define LDD_ADC_CHANNEL_39_PIN 0x80u /*!< Channel 39 pin mask */
+#define LDD_ADC_CHANNEL_40_PIN 0x0100u /*!< Channel 40 pin mask */
+#define LDD_ADC_CHANNEL_41_PIN 0x0200u /*!< Channel 41 pin mask */
+#define LDD_ADC_CHANNEL_42_PIN 0x0400u /*!< Channel 42 pin mask */
+#define LDD_ADC_CHANNEL_43_PIN 0x0800u /*!< Channel 43 pin mask */
+#define LDD_ADC_CHANNEL_44_PIN 0x1000u /*!< Channel 44 pin mask */
+#define LDD_ADC_CHANNEL_45_PIN 0x2000u /*!< Channel 45 pin mask */
+#define LDD_ADC_CHANNEL_46_PIN 0x4000u /*!< Channel 46 pin mask */
+#define LDD_ADC_CHANNEL_47_PIN 0x8000u /*!< Channel 47 pin mask */
+#define LDD_ADC_CHANNEL_48_PIN 0x00010000u /*!< Channel 48 pin mask */
+#define LDD_ADC_CHANNEL_49_PIN 0x00020000u /*!< Channel 49 pin mask */
+#define LDD_ADC_CHANNEL_50_PIN 0x00040000u /*!< Channel 50 pin mask */
+#define LDD_ADC_CHANNEL_51_PIN 0x00080000u /*!< Channel 51 pin mask */
+#define LDD_ADC_CHANNEL_52_PIN 0x00100000u /*!< Channel 52 pin mask */
+#define LDD_ADC_CHANNEL_53_PIN 0x00200000u /*!< Channel 53 pin mask */
+#define LDD_ADC_CHANNEL_54_PIN 0x00400000u /*!< Channel 54 pin mask */
+#define LDD_ADC_CHANNEL_55_PIN 0x00800000u /*!< Channel 55 pin mask */
+#define LDD_ADC_CHANNEL_56_PIN 0x01000000u /*!< Channel 56 pin mask */
+#define LDD_ADC_CHANNEL_57_PIN 0x02000000u /*!< Channel 57 pin mask */
+#define LDD_ADC_CHANNEL_58_PIN 0x04000000u /*!< Channel 58 pin mask */
+#define LDD_ADC_CHANNEL_59_PIN 0x08000000u /*!< Channel 59 pin mask */
+#define LDD_ADC_CHANNEL_60_PIN 0x10000000u /*!< Channel 60 pin mask */
+#define LDD_ADC_CHANNEL_61_PIN 0x20000000u /*!< Channel 61 pin mask */
+#define LDD_ADC_CHANNEL_62_PIN 0x40000000u /*!< Channel 62 pin mask */
+#define LDD_ADC_CHANNEL_63_PIN 0x80000000u /*!< Channel 63 pin mask */
+
+#define LDD_ADC_TRIGGER_0_PIN 0x01u /*!< Trigger 0 pin mask */
+#define LDD_ADC_TRIGGER_1_PIN 0x02u /*!< Trigger 1 pin mask */
+
+#define LDD_ADC_LOW_VOLT_REF_PIN 0x01u /*!< Low voltage reference pin mask */
+#define LDD_ADC_HIGH_VOLT_REF_PIN 0x02u /*!< High voltage reference pin mask */
+
+#define LDD_ADC_ON_MEASUREMENT_COMPLETE 0x40u /*!< OnMeasurementComplete event mask */
+#define LDD_ADC_ON_ERROR 0x80u /*!< OnError event mask */
+
+#define LDD_ADC_DMA_ERROR 0x01u /*!< DMA error mask */
+
+typedef uint32_t LDD_ADC_TErrorMask; /*!< ADC error type */
+
+/*! Structure pins for pin connection method */
+typedef struct {
+ uint32_t Channel0_31PinMask; /*!< Channel pin mask for channels 0 through 31 */
+ uint32_t Channel32_63PinMask; /*!< Channel pin mask for channels 32 through 63 */
+ uint16_t TriggerPinMask; /*!< Trigger pin mask */
+ uint8_t VoltRefPinMask; /*!< Voltage reference pin mask */
+} LDD_ADC_TPinMask;
+
+/*! Structure used to describing one sample */
+typedef struct {
+ uint8_t ChannelIdx; /*!< Channel index */
+} LDD_ADC_TSample;
+
+/*! Type specifying the ADC compare mode */
+typedef enum {
+ LDD_ADC_LESS_THAN = 0x00u, /*!< Compare true if the result is less than the Low compare value */
+ LDD_ADC_GREATER_THAN_OR_EQUAL = 0x01u, /*!< Compare true if the result is greater than or equal to Low compare value */
+ LDD_ADC_INSIDE_RANGE_INCLUSIVE = 0x02u, /*!< Compare true if the result is greater than or equal to Low compare value and the result is less than or equal to High compare value */
+ LDD_ADC_INSIDE_RANGE_NOT_INCLUSIVE = 0x03u, /*!< Compare true if the result is greater than Low compare value and the result is less than High compare value */
+ LDD_ADC_OUTSIDE_RANGE_INCLUSIVE = 0x04u, /*!< Compare true if the result is less than or equal to Low compare value or the result is greater than or equal to High compare value */
+ LDD_ADC_OUTSIDE_RANGE_NOT_INCLUSIVE = 0x05u /*!< Compare true if the result is less than Low compare value or the result is greater than High compare value */
+} LDD_ADC_TCompareMode;
+
+/*
+** ===================================================================
+** I2C device types and constants
+** ===================================================================
+*/
+
+#define LDD_I2C_SDA_PIN 0x01u /*!< SDA pin mask */
+#define LDD_I2C_SCL_PIN 0x02u /*!< SCL pin mask */
+
+#define LDD_I2C_ON_MASTER_BLOCK_SENT 0x0001u /*!< OnMasterBlockSent event mask */
+#define LDD_I2C_ON_MASTER_BLOCK_RECEIVED 0x0002u /*!< OnMasterBlockReceived event mask */
+#define LDD_I2C_ON_SLAVE_BLOCK_SENT 0x0004u /*!< OnSlaveBlockSent event mask */
+#define LDD_I2C_ON_SLAVE_BLOCK_RECEIVED 0x0008u /*!< OnSlaveBlockReceived event mask */
+#define LDD_I2C_ON_SLAVE_TX_REQUEST 0x0010u /*!< OnSlaveTxRequest event mask */
+#define LDD_I2C_ON_SLAVE_RX_REQUEST 0x0020u /*!< OnSlaveRxRequest event mask */
+#define LDD_I2C_ON_ERROR 0x0040u /*!< OnError event mask */
+#define LDD_I2C_ON_SLAVE_SM_BUS_CALL_ADDR 0x0080u /*!< OnSlaveSMBusCallAddr event mask */
+#define LDD_I2C_ON_SLAVE_SM_BUS_ALERT_RESPONSE 0x0100u /*!< OnSlaveSMBusAlertResponse event mask */
+#define LDD_I2C_ON_SLAVE_GENERAL_CALL_ADDR 0x0200u /*!< OnSlaveGeneralCallAddr event mask */
+#define LDD_I2C_ON_MASTER_BYTE_RECEIVED 0x0400u /*!< OnMasterByteReceived event mask */
+#define LDD_I2C_ON_SLAVE_BYTE_RECEIVED 0x0800u /*!< OnMasterByteReceived event mask */
+#define LDD_I2C_ON_BUS_START_DETECTED 0x1000u /*!< OnBusStartDetected event mask */
+#define LDD_I2C_ON_BUS_STOP_DETECTED 0x2000u /*!< OnBusStopDetected event mask */
+
+#define LDD_I2C_SLAVE_TX_UNDERRUN 0x0001u /*!< SlaveTxUnderrun error mask */
+#define LDD_I2C_SLAVE_RX_OVERRUN 0x0002u /*!< SlaveRxOverrun error mask */
+#define LDD_I2C_ARBIT_LOST 0x0004u /*!< ArbitLost error mask */
+#define LDD_I2C_MASTER_NACK 0x0008u /*!< MasterNACK error mask */
+#define LDD_I2C_SCL_LOW_TIMEOUT 0x0010u /*!< SCLLowTimeout error mask */
+#define LDD_I2C_SDA_LOW_TIMEOUT 0x0020u /*!< SDALowTimeout error mask */
+#define LDD_I2C_SLAVE_NACK 0x0040u /*!< SlaveNACK error mask */
+
+typedef uint16_t LDD_I2C_TSize; /*!< Type specifying the length of the data or buffer. */
+typedef uint16_t LDD_I2C_TAddr; /*!< Type specifying the address variable */
+typedef uint16_t LDD_I2C_TErrorMask; /*!< Type specifying the error mask type. */
+typedef bool LDD_I2C_TMode; /*!< Type specifynng the Actual operating mode */
+
+/*! Type specifying the address type */
+typedef enum {
+ LDD_I2C_ADDRTYPE_7BITS, /*!< 7 bits address */
+ LDD_I2C_ADDRTYPE_10BITS, /*!< 10 bits address */
+ LDD_I2C_ADDRTYPE_GENERAL_CALL /*!< General call address */
+} LDD_I2C_TAddrType;
+
+/*! Type specifying generate the stop condition */
+typedef enum {
+ LDD_I2C_NO_SEND_STOP, /*!< Do not send stop signal */
+ LDD_I2C_SEND_STOP /*!< Send stop signal */
+} LDD_I2C_TSendStop;
+
+/*! Type specifying the I2C state of BUS. */
+typedef enum {
+ LDD_I2C_BUSY, /*!< The bus is busy */
+ LDD_I2C_IDLE /*!< The bus is idle */
+} LDD_I2C_TBusState;
+
+/*! Type specifying the I2C byte acknowledge response. */
+typedef enum {
+ LDD_I2C_ACK_BYTE, /*!< Byte acknowledged */
+ LDD_I2C_NACK_BYTE /*!< Byte not acknowledged */
+} LDD_I2C_TAckType;
+
+/*! Communication statistics */
+typedef struct {
+ uint32_t MasterSentChars; /*!< Number of master transmitted characters. */
+ uint32_t MasterReceivedChars; /*!< Number of master received characters. */
+ uint32_t MasterNacks; /*!< Number of no acknowledges. */
+ uint32_t ArbitLost; /*!< Number of lost the bus arbitration. */
+ uint32_t SlaveSentChars; /*!< Number of slave transmitted characters. */
+ uint32_t SlaveReceivedChars; /*!< Number of slave received characters. */
+ uint32_t SlaveTxUnderrun; /*!< Number of slave underrun. */
+ uint32_t SlaveRxOverrun; /*!< Number of slave overrun. */
+ uint32_t SlaveGeneralCallAddr; /*!< Number of a general call address. */
+ uint32_t SlaveSmBusCallAddr; /*!< Number of a SMBus call address. */
+ uint32_t SlaveSmBusAlertResponse; /*!< Number of slave SMBus alert response received. */
+ uint32_t SCLLowTimeout; /*!< Number of SCL low timeout occur. */
+ uint32_t SDALowTimeout; /*!< Number of SCL low timeout occur. */
+} LDD_I2C_TStats;
+
+
+/*
+** ===================================================================
+** SegLCD device types and constants
+** ===================================================================
+*/
+
+#define LDD_SEGLCD_ON_FRAME_FREQUENCY 0x0001u /*!< OnFrameFrequency event mask */
+#define LDD_SEGLCD_ON_FAULT_DETECT_COMPLETE 0x0002u /*!< OnFaultDetectComplete event mask */
+
+typedef uint8_t LDD_SegLCD_TPinIndex; /*!< Type specifying the segment LCD pin index variable */
+typedef uint8_t LDD_SegLCD_TFrontplaneData; /*!< Type specifying the frontplane/backplane segment variable */
+typedef uint8_t LDD_SegLCD_TFaultValue; /*!< Type specifying the frontplane/backplane segment variable */
+
+/*! Types specifying the segment LCD blinking. */
+typedef enum {
+ LDD_SEGLCD_BLINK_OFF, /*!< Disables display blinking */
+ LDD_SEGLCD_BLINK_ALL, /*!< Display blank during the blink period */
+ LDD_SEGLCD_BLINK_ALL_ALTERNATE /*!< Blinking between alternate backplane */
+} LDD_SegLCD_TBlinking;
+
+/*! Segment LCD blank state type. */
+typedef enum {
+ LDD_SEGLCD_BLANK_STATE, /*!< Blank display mode */
+ LDD_SEGLCD_NORMAL_STATE, /*!< Normal display mode */
+ LDD_SEGLCD_ALTERNATE_STATE /*!< Alternate display mode */
+} LDD_SegLCD_TSetBlank;
+
+/*! Segment LCD pin type (frontplane/backplane) */
+typedef enum {
+ LDD_SEGLCD_BACKPLANE_PIN, /*!< Backplane pin */
+ LDD_SEGLCD_FRONTPLANE_PIN /*!< Frontplane pin */
+} LDD_SegLCD_TPinType;
+
+
+/*
+** ===================================================================
+** GPIO device types and constants
+** ===================================================================
+*/
+
+#define LDD_GPIO_PIN_0 0x01u /*!< Pin 0 inside the port */
+#define LDD_GPIO_PIN_1 0x02u /*!< Pin 1 inside the port */
+#define LDD_GPIO_PIN_2 0x04u /*!< Pin 2 inside the port */
+#define LDD_GPIO_PIN_3 0x08u /*!< Pin 3 inside the port */
+#define LDD_GPIO_PIN_4 0x10u /*!< Pin 4 inside the port */
+#define LDD_GPIO_PIN_5 0x20u /*!< Pin 5 inside the port */
+#define LDD_GPIO_PIN_6 0x40u /*!< Pin 6 inside the port */
+#define LDD_GPIO_PIN_7 0x80u /*!< Pin 7 inside the port */
+#define LDD_GPIO_PIN_8 0x0100u /*!< Pin 8 inside the port */
+#define LDD_GPIO_PIN_9 0x0200u /*!< Pin 9 inside the port */
+#define LDD_GPIO_PIN_10 0x0400u /*!< Pin 10 inside the port */
+#define LDD_GPIO_PIN_11 0x0800u /*!< Pin 11 inside the port */
+#define LDD_GPIO_PIN_12 0x1000u /*!< Pin 12 inside the port */
+#define LDD_GPIO_PIN_13 0x2000u /*!< Pin 13 inside the port */
+#define LDD_GPIO_PIN_14 0x4000u /*!< Pin 14 inside the port */
+#define LDD_GPIO_PIN_15 0x8000u /*!< Pin 15 inside the port */
+#define LDD_GPIO_PIN_16 0x00010000u /*!< Pin 16 inside the port */
+#define LDD_GPIO_PIN_17 0x00020000u /*!< Pin 17 inside the port */
+#define LDD_GPIO_PIN_18 0x00040000u /*!< Pin 18 inside the port */
+#define LDD_GPIO_PIN_19 0x00080000u /*!< Pin 19 inside the port */
+#define LDD_GPIO_PIN_20 0x00100000u /*!< Pin 20 inside the port */
+#define LDD_GPIO_PIN_21 0x00200000u /*!< Pin 21 inside the port */
+#define LDD_GPIO_PIN_22 0x00400000u /*!< Pin 22 inside the port */
+#define LDD_GPIO_PIN_23 0x00800000u /*!< Pin 23 inside the port */
+#define LDD_GPIO_PIN_24 0x01000000u /*!< Pin 24 inside the port */
+#define LDD_GPIO_PIN_25 0x02000000u /*!< Pin 25 inside the port */
+#define LDD_GPIO_PIN_26 0x04000000u /*!< Pin 26 inside the port */
+#define LDD_GPIO_PIN_27 0x08000000u /*!< Pin 27 inside the port */
+#define LDD_GPIO_PIN_28 0x10000000u /*!< Pin 28 inside the port */
+#define LDD_GPIO_PIN_29 0x20000000u /*!< Pin 29 inside the port */
+#define LDD_GPIO_PIN_30 0x40000000u /*!< Pin 30 inside the port */
+#define LDD_GPIO_PIN_31 0x80000000u /*!< Pin 31 inside the port */
+
+#define LDD_GPIO_ON_PORT_EVENT 0x01u /*!< OnPortEvent event mask */
+
+typedef uint32_t LDD_GPIO_TBitField; /*!< Abstract type specifying the bit field within the port. */
+
+/*! Defines condition when event is invoked. */
+typedef enum {
+ LDD_GPIO_DISABLED = 0x00u, /*!< Event doesn't invoke */
+ LDD_GPIO_LOW = 0x00080000u, /*!< Event when logic zero */
+ LDD_GPIO_HIGH = 0x000C0000u, /*!< Event when logic one */
+ LDD_GPIO_RISING = 0x00090000u, /*!< Event on rising edge */
+ LDD_GPIO_FALLING = 0x000A0000u, /*!< Event on falling edge */
+ LDD_GPIO_BOTH = 0x000B0000u /*!< Event on rising and falling edge */
+} LDD_GPIO_TEventCondition; /*!< Defines condition when event is invoked. */
+
+#define LDD_GPIO_EVENT_CONDITIONS_MASK 0x000F0000u
+
+/*
+** ===================================================================
+** BITSIO device types and constants
+** ===================================================================
+*/
+#define LDD_BITSIO_PIN_0 0x01U /*!< Pin 0 inside pin list of component */
+#define LDD_BITSIO_PIN_1 0x02U /*!< Pin 1 inside pin list of component */
+#define LDD_BITSIO_PIN_2 0x04U /*!< Pin 2 inside pin list of component */
+#define LDD_BITSIO_PIN_3 0x08U /*!< Pin 3 inside pin list of component */
+#define LDD_BITSIO_PIN_4 0x10U /*!< Pin 4 inside pin list of component */
+#define LDD_BITSIO_PIN_5 0x20U /*!< Pin 5 inside pin list of component */
+#define LDD_BITSIO_PIN_6 0x40U /*!< Pin 6 inside pin list of component */
+#define LDD_BITSIO_PIN_7 0x80U /*!< Pin 7 inside pin list of component */
+#define LDD_BITSIO_PIN_8 0x0100U /*!< Pin 8 inside pin list of component */
+#define LDD_BITSIO_PIN_9 0x0200U /*!< Pin 9 inside pin list of component */
+#define LDD_BITSIO_PIN_10 0x0400U /*!< Pin 10 inside pin list of component */
+#define LDD_BITSIO_PIN_11 0x0800U /*!< Pin 11 inside pin list of component */
+#define LDD_BITSIO_PIN_12 0x1000U /*!< Pin 12 inside pin list of component */
+#define LDD_BITSIO_PIN_13 0x2000U /*!< Pin 13 inside pin list of component */
+#define LDD_BITSIO_PIN_14 0x4000U /*!< Pin 14 inside pin list of component */
+#define LDD_BITSIO_PIN_15 0x8000U /*!< Pin 15 inside pin list of component */
+#define LDD_BITSIO_PIN_16 0x00010000U /*!< Pin 16 inside pin list of component */
+#define LDD_BITSIO_PIN_17 0x00020000U /*!< Pin 17 inside pin list of component */
+#define LDD_BITSIO_PIN_18 0x00040000U /*!< Pin 18 inside pin list of component */
+#define LDD_BITSIO_PIN_19 0x00080000U /*!< Pin 19 inside pin list of component */
+#define LDD_BITSIO_PIN_20 0x00100000U /*!< Pin 20 inside pin list of component */
+#define LDD_BITSIO_PIN_21 0x00200000U /*!< Pin 21 inside pin list of component */
+#define LDD_BITSIO_PIN_22 0x00400000U /*!< Pin 22 inside pin list of component */
+#define LDD_BITSIO_PIN_23 0x00800000U /*!< Pin 23 inside pin list of component */
+#define LDD_BITSIO_PIN_24 0x01000000U /*!< Pin 24 inside pin list of component */
+#define LDD_BITSIO_PIN_25 0x02000000U /*!< Pin 25 inside pin list of component */
+#define LDD_BITSIO_PIN_26 0x04000000U /*!< Pin 26 inside pin list of component */
+#define LDD_BITSIO_PIN_27 0x08000000U /*!< Pin 27 inside pin list of component */
+#define LDD_BITSIO_PIN_28 0x10000000U /*!< Pin 28 inside pin list of component */
+#define LDD_BITSIO_PIN_29 0x20000000U /*!< Pin 29 inside pin list of component */
+#define LDD_BITSIO_PIN_30 0x40000000U /*!< Pin 30 inside pin list of component */
+#define LDD_BITSIO_PIN_31 0x80000000U /*!< Pin 31 inside pin list of component */
+
+/*
+** ===================================================================
+** Ethernet device types and constants
+** ===================================================================
+*/
+
+#define LDD_ETH_MDC_PIN 0x01u /*!< MDC pin mask */
+#define LDD_ETH_MDIO_PIN 0x02u /*!< MDIO pin mask */
+#define LDD_ETH_COL_PIN 0x04u /*!< COL pin mask */
+#define LDD_ETH_CRS_PIN 0x08u /*!< CRS pin mask */
+#define LDD_ETH_TXCLK_PIN 0x10u /*!< TXCLK pin mask */
+#define LDD_ETH_TXD0_PIN 0x20u /*!< TXD0 pin mask */
+#define LDD_ETH_TXD1_PIN 0x40u /*!< TXD1 pin mask */
+#define LDD_ETH_TXD2_PIN 0x80u /*!< TXD2 pin mask */
+#define LDD_ETH_TXD3_PIN 0x0100u /*!< TXD3 pin mask */
+#define LDD_ETH_TXEN_PIN 0x0200u /*!< TXEN pin mask */
+#define LDD_ETH_TXER_PIN 0x0400u /*!< TXER pin mask */
+#define LDD_ETH_RXCLK_PIN 0x0800u /*!< RXCLK pin mask */
+#define LDD_ETH_RXDV_PIN 0x1000u /*!< RXDV pin mask */
+#define LDD_ETH_RXD0_PIN 0x2000u /*!< RXD0 pin mask */
+#define LDD_ETH_RXD1_PIN 0x4000u /*!< RXD1 pin mask */
+#define LDD_ETH_RXD2_PIN 0x8000u /*!< RXD2 pin mask */
+#define LDD_ETH_RXD3_PIN 0x00010000u /*!< RXD3 pin mask */
+#define LDD_ETH_RXER_PIN 0x00020000u /*!< RXER pin mask */
+
+#define LDD_ETH_ON_FRAME_TRANSMITTED 0x01u /*!< OnFrameTransmitted event mask */
+#define LDD_ETH_ON_FRAME_TRANSMITTED_TIMESTAMPED 0x02u /*!< OnFrameTransmittedTimestamped event mask */
+#define LDD_ETH_ON_FRAME_RECEIVED 0x04u /*!< OnFrameReceived event mask */
+#define LDD_ETH_ON_FRAME_RECEIVED_TIMESTAMPED 0x08u /*!< OnFrameReceivedTimestamped event mask */
+#define LDD_ETH_ON_MII_FINISHED 0x10u /*!< OnMIIFinished event mask */
+#define LDD_ETH_ON_FATAL_ERROR 0x20u /*!< OnFatalError event mask */
+#define LDD_ETH_ON_WAKE_UP 0x40u /*!< OnWakeUp event mask */
+
+typedef uint8_t LDD_ETH_TMACAddress[6]; /*!< Ethernet MAC address */
+
+/*! Ethernet duplex mode */
+typedef enum {
+ LDD_ETH_FULL_DUPLEX, /*!< Full duplex mode */
+ LDD_ETH_HALF_DUPLEX /*!< Half duplex mode */
+} LDD_ETH_TDuplexMode;
+
+/*! Ethernet address filter mode options */
+typedef enum {
+ LDD_ETH_PROMISC, /*!< Promiscuous mode */
+ LDD_ETH_REJECT_BC, /*!< Reject broadcast frames */
+ LDD_ETH_ACCEPT_BC /*!< Accept broadcast frames */
+} LDD_ETH_TFilterMode;
+
+/*! Ethernet sleep mode options */
+typedef enum {
+ LDD_ETH_ENABLED, /*!< Sleep mode enabled */
+ LDD_ETH_ENABLED_WITH_WAKEUP, /*!< Sleep mode enabled, waiting for wake-up */
+ LDD_ETH_DISABLED /*!< Sleep mode disabled */
+} LDD_ETH_TSleepMode;
+
+/*! Ethernet frame buffer (fragment) descriptor */
+typedef struct {
+ uint8_t *DataPtr; /*!< Pointer to buffer data */
+ uint16_t Size; /*!< Buffer data size */
+} LDD_ETH_TBufferDesc;
+
+typedef LDD_ETH_TBufferDesc* LDD_ETH_TBufferDescPtr; /*!< Frame buffer descriptor pointer type */
+
+/*! Ethernet communication statistics */
+typedef struct {
+ uint32_t TxRMONDropEvents; /*!< Count of frames not counted correctly */
+ uint32_t TxRMONOctets; /*!< Octet count for frames transmitted without error */
+ uint32_t TxRMONPackets; /*!< Transmitted packet count */
+ uint32_t TxRMONBroadcastPackets; /*!< Transmitted broadcast packets */
+ uint32_t TxRMONMulticastPackets; /*!< Transmitted multicast packets */
+ uint32_t TxRMONCRCAlignErrors; /*!< Transmitted packets with CRC or alignment error */
+ uint32_t TxRMONUndersizePackets; /*!< Transmitted packets smaller than 64 bytes with good CRC */
+ uint32_t TxRMONOversizePackets; /*!< Transmitted packets greater than max. frame length with good CRC */
+ uint32_t TxRMONFragments; /*!< Transmitted packets smaller than 64 bytes with bad CRC */
+ uint32_t TxRMONJabbers; /*!< Transmitted packets greater than max. frame length with bad CRC */
+ uint32_t TxRMONCollisions; /*!< Transmit collision count */
+ uint32_t TxRMONPackets64Octets; /*!< Transmitted 64 byte packets */
+ uint32_t TxRMONPackets65To127Octets; /*!< Transmitted 65 to 127 byte packets */
+ uint32_t TxRMONPackets128To255Octets; /*!< Transmitted 128 to 255 byte packets */
+ uint32_t TxRMONPackets256To511Octets; /*!< Transmitted 256 to 511 byte packets */
+ uint32_t TxRMONPackets512To1023Octets; /*!< Transmitted 512 to 1023 byte packets */
+ uint32_t TxRMONPackets1024To2047Octets; /*!< Transmitted 1024 to 2047 byte packets */
+ uint32_t TxRMONPacketsGreaterThan2048Octets; /*!< Transmitted packets greater than 2048 byte */
+ uint32_t TxIEEEDrop; /*!< Count of frames not counted correctly */
+ uint32_t TxIEEEFrameOK; /*!< Frames transmitted OK */
+ uint32_t TxIEEESingleCollision; /*!< Frames transmitted with single collision */
+ uint32_t TxIEEEMultipleCollisions; /*!< Frames transmitted with multiple collisions */
+ uint32_t TxIEEEDeferralDelay; /*!< Frames transmitted after deferral delay */
+ uint32_t TxIEEELateCollision; /*!< Frames transmitted with late collision */
+ uint32_t TxIEEEExcessiveCollision; /*!< Frames transmitted with excessive collisions */
+ uint32_t TxIEEEFIFOUnderrun; /*!< Frames transmitted with transmit FIFO underrun */
+ uint32_t TxIEEECarrierSenseError; /*!< Frames transmitted with carrier sense error */
+ uint32_t TxIEEESQEError; /*!< Frames transmitted with SQE error */
+ uint32_t TxIEEEPauseFrame; /*!< Flow control pause frames transmitted */
+ uint32_t TxIEEEOctetsOK; /*!< Octet count for frames transmitted without error */
+ uint32_t RxRMONDropEvents; /*!< Count of frames not counted correctly */
+ uint32_t RxRMONOctets; /*!< Octet count for frames recieved without error */
+ uint32_t RxRMONPackets; /*!< Received packet count */
+ uint32_t RxRMONBroadcastPackets; /*!< Received broadcast packets */
+ uint32_t RxRMONMulticastPackets; /*!< Received multicast packets */
+ uint32_t RxRMONCRCAlignErrors; /*!< Received packets with CRC or alignment error */
+ uint32_t RxRMONUndersizePackets; /*!< Received packets smaller than 64 bytes with good CRC */
+ uint32_t RxRMONOversizePackets; /*!< Received packets greater than max. frame length with good CRC */
+ uint32_t RxRMONFragments; /*!< Received packets smaller than 64 bytes with bad CRC */
+ uint32_t RxRMONJabbers; /*!< Received packets greater than max. frame length with bad CRC */
+ uint32_t RxRMONPackets64Octets; /*!< Received 64 byte packets */
+ uint32_t RxRMONPackets65To127Octets; /*!< Received 65 to 127 byte packets */
+ uint32_t RxRMONPackets128To255Octets; /*!< Received 128 to 255 byte packets */
+ uint32_t RxRMONPackets256To511Octets; /*!< Received 256 to 511 byte packets */
+ uint32_t RxRMONPackets512To1023Octets; /*!< Received 512 to 1023 byte packets */
+ uint32_t RxRMONPackets1024To2047Octets; /*!< Received 1024 to 2047 byte packets */
+ uint32_t RxRMONPacketsGreaterThan2048Octets; /*!< Received packets greater than 2048 byte */
+ uint32_t RxIEEEDrop; /*!< Count of frames not counted correctly */
+ uint32_t RxIEEEFrameOK; /*!< Frames received OK */
+ uint32_t RxIEEECRCError; /*!< Frames received with CRC error */
+ uint32_t RxIEEEAlignmentError; /*!< Frames received with alignment error */
+ uint32_t RxIEEEFIFOOverflow; /*!< Receive FIFO overflow count */
+ uint32_t RxIEEEPauseFrame; /*!< Flow control pause frames received */
+ uint32_t RxIEEEOctetsOK; /*!< Octet count for frames received without error */
+} LDD_ETH_TStats;
+
+/*
+** ===================================================================
+** FlexCAN device types and constants
+** ===================================================================
+*/
+
+typedef uint8_t LDD_CAN_TMBIndex; /*!< CAN message buffer index */
+typedef uint32_t LDD_CAN_TAccMask; /*!< Type specifying the acceptance mask variable. */
+typedef uint32_t LDD_CAN_TMessageID; /*!< Type specifying the ID mask variable. */
+typedef uint8_t LDD_CAN_TErrorCounter; /*!< Type specifying the error counter variable. */
+typedef uint32_t LDD_CAN_TErrorMask; /*!< Type specifying the error mask variable. */
+typedef uint16_t LDD_CAN_TBufferMask; /*!< Type specifying the message buffer mask variable. */
+#define LDD_CAN_RX_PIN 0x01U /*!< Rx pin mask */
+#define LDD_CAN_TX_PIN 0x02U /*!< Tx pin mask */
+
+#define LDD_CAN_ON_FULL_RXBUFFER 0x01U /*!< OnFullRxBuffer event mask */
+#define LDD_CAN_ON_FREE_TXBUFFER 0x02U /*!< OnFreeTxBuffer event mask */
+#define LDD_CAN_ON_BUSOFF 0x04U /*!< OnBusOff event mask */
+#define LDD_CAN_ON_TXWARNING 0x08U /*!< OnTransmitterWarning event mask */
+#define LDD_CAN_ON_RXWARNING 0x10U /*!< OnReceiverWarning event mask */
+#define LDD_CAN_ON_ERROR 0x20U /*!< OnError event mask */
+#define LDD_CAN_ON_WAKEUP 0x40U /*!< OnWakeUp event mask */
+
+#define LDD_CAN_BIT0_ERROR 0x4000UL /*!< Bit0 error detect error mask */
+#define LDD_CAN_BIT1_ERROR 0x8000UL /*!< Bit1 error detect error mask */
+#define LDD_CAN_ACK_ERROR 0x2000UL /*!< Acknowledge error detect error mask */
+#define LDD_CAN_CRC_ERROR 0x1000UL /*!< Cyclic redundancy check error detect error mask */
+#define LDD_CAN_FORM_ERROR 0x0800UL /*!< Message form error detect error mask */
+#define LDD_CAN_STUFFING_ERROR 0x0400UL /*!< Bit stuff error detect error mask */
+
+#define LDD_CAN_MESSAGE_ID_EXT 0x80000000UL /*!< Value specifying extended Mask, ID */
+
+/*! Type specifying the CAN frame type. */
+typedef enum {
+ LDD_CAN_MB_RX_NOT_ACTIVE = 0x00U,
+ LDD_CAN_MB_RX_FULL = 0x02U,
+ LDD_CAN_MB_RX_EMPTY = 0x04U,
+ LDD_CAN_MB_RX_OVERRUN = 0x06U,
+ LDD_CAN_MB_RX_BUSY = 0x01U,
+ LDD_CAN_MB_RX_RANSWER = 0x0AU
+} LDD_CAN_TRxBufferState;
+
+/*! Type specifying the CAN frame type. */
+typedef enum {
+ LDD_CAN_DATA_FRAME, /*!< Data frame type received or transmitted */
+ LDD_CAN_REMOTE_FRAME, /*!< Remote frame type */
+ LDD_CAN_RESPONSE_FRAME /*!< Response frame type - Tx buffer send data after receiving remote frame with the same ID */
+} LDD_CAN_TFrameType;
+
+/*! Type specifying the CAN communication statistics. */
+typedef struct {
+ uint32_t TxFrames; /*!< Transmitted frame counter */
+ uint32_t TxWarnings; /*!< Transmission warning counter */
+ uint32_t RxFrames; /*!< Received frame counter */
+ uint32_t RxWarnings; /*!< Reception warning counter */
+ uint32_t BusOffs; /*!< Bus off counter */
+ uint32_t Wakeups; /*!< Wakeup counter */
+ uint32_t Bit0Errors; /*!< Bit0 error counter */
+ uint32_t Bit1Errors; /*!< Bit1 error counter */
+ uint32_t AckErrors; /*!< ACK error counter */
+ uint32_t CrcErrors; /*!< CRC error counter */
+ uint32_t FormErrors; /*!< Message form error counter */
+ uint32_t BitStuffErrors; /*!< Bit stuff error counter */
+ uint32_t Errors; /*!< Error counter */
+} LDD_CAN_TStats;
+
+/*! Type specifying the CAN frame features. */
+typedef struct {
+ LDD_CAN_TMessageID MessageID; /*!< Message ID */
+ LDD_CAN_TFrameType FrameType; /*!< Type of the frame DATA/REMOTE */
+ uint8_t *Data; /*!< Message data buffer */
+ uint8_t Length; /*!< Message length */
+ uint16_t TimeStamp; /*!< Message time stamp */
+ uint8_t LocPriority; /*!< Local Priority Tx Buffers */
+} LDD_CAN_TFrame;
+
+/*
+** ===================================================================
+** USB device types and constants
+** ===================================================================
+*/
+
+/* Events' masks */
+#define LDD_USB_ON_DEVICE_RESET 0x00000001u /*!< OnDeviceReset event mask */
+#define LDD_USB_ON_DEVICE_SPEED_DETECT 0x00000002u /*!< OnDeviceSpeedDetect event mask */
+#define LDD_USB_ON_DEVICE_SUSPEND 0x00000004u /*!< OnDeviceSuspend event mask */
+#define LDD_USB_ON_DEVICE_RESUME 0x00000008u /*!< OnDeviceResume event mask */
+#define LDD_USB_ON_DEVICE_SETUP_PACKET 0x00000010u /*!< OnDeviceSetupPacket event mask */
+#define LDD_USB_ON_DEVICE_SOF 0x00000020u /*!< OnDeviceSof event mask */
+#define LDD_USB_ON_DEVICE_1MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */
+#define LDD_USB_ON_DEVICE_1_MS_TIMER 0x00000040u /*!< OnDevice1msTimer event mask */
+#define LDD_USB_ON_DEVICE_ERROR 0x00000080u /*!< OnDeviceError event mask */
+#define LDD_USB_ON_HOST_DEVICE_DEATTACH 0x00000100u /*!< OnHostDeviceAttach event mask */
+#define LDD_USB_ON_HOST_RESET_RECOVERY 0x00000200u /*!< OnHostResetRecovery event mask */
+#define LDD_USB_ON_HOST_RESUME_RECOVERY 0x00000400u /*!< OnHostResumeRecovery event mask */
+#define LDD_USB_ON_HOST_1MS_TIMER 0x00000800u /*!< 1 ms timer event mask */
+#define LDD_USB_ON_HOST_1_MS_TIMER 0x00000800u /*!< 1 ms timer event mask */
+#define LDD_USB_ON_HOST_ERROR 0x00001000u /*!< OnHostError event mask */
+#define LDD_USB_ON_OTG_DEVICE 0x00002000u /*!< OnOtgDevice event mask */
+#define LDD_USB_ON_OTG_HOST 0x00004000u /*!< OnOtgHost event mask */
+#define LDD_USB_ON_OTG_STATE_CHANGE 0x00008000u /*!< OnOtgStageChange event mask */
+#define LDD_USB_ON_SIGNAL_CHANGE 0x00010000u /*!< OnSignalChange event mask */
+
+/* Data pins' masks */
+#define LDD_USB_DP_PIN 0x00000001u /*!< Data+ pin mask */
+#define LDD_USB_DM_PIN 0x00000002u /*!< Data- pin mask */
+
+/* Pullup/pulldown pin masks */
+#define LDD_USB_DP_PU_PIN 0x00000004u /*!< Data+ pull-up pin mask */
+#define LDD_USB_DM_PU_PIN 0x00000008u /*!< Data- pull-up pin mask */
+#define LDD_USB_DP_PD_PIN 0x00000010u /*!< Data+ pull-down pin mask */
+#define LDD_USB_DM_PD_PIN 0x00000020u /*!< Data- pull-down pin mask */
+
+/* VBUS pins' mask */
+#define LDD_USB_DEVICE_VBUS_DETECT_PIN 0x00000040u /*!< VBUS detect pin mask */
+#define LDD_USB_HOST_VBUS_ENABLE_PIN 0x00000080u /*!< VBUS enable pin mask */
+#define LDD_USB_HOST_VBUS_OVERCURRENT_PIN 0x00000100u /*!< VBUS overcurrent pin mask */
+
+/* OTG pins' masks */
+#define LDD_USB_OTG_ID_PIN 0x00000200u /*!< ID pin mask */
+#define LDD_USB_OTG_VBUS_VALID_PIN 0x00000400u /*!< VBUS valid pin mask */
+#define LDD_USB_OTG_SESSION_VALID_PIN 0x00000800u /*!< SESSION valid pin mask */
+#define LDD_USB_OTG_B_SESSION_END_PIN 0x00004000u /*!< B SESSION end pin mask */
+#define LDD_USB_OTG_VBUS_ENABLE_PIN 0x00008000u /*!< VBUS drive pin mask */
+#define LDD_USB_OTG_VBUS_CHARGE_PIN 0x00010000u /*!< VBUS charge pin mask */
+#define LDD_USB_OTG_VBUS_DISCHARGE_PIN 0x00020000u /*!< VBUS discharge pin mask */
+
+/* ULPI pins' masks */
+#define LDD_USB_ULPI_CLK_PIN 0x00080000u /*!< ULPI_CLK pin mask */
+#define LDD_USB_ULPI_DIR_PIN 0x00100000u /*!< ULPI_DIR pin mask */
+#define LDD_USB_ULPI_NXT_PIN 0x00200000u /*!< ULPI_NXT pin mask */
+#define LDD_USB_ULPI_STP_PIN 0x00400000u /*!< ULPI_STOP pin mask */
+#define LDD_USB_ULPI_DATA_0_PIN 0x00800000u /*!< ULPI_DATA_0 pin mask */
+#define LDD_USB_ULPI_DATA_1_PIN 0x01000000u /*!< ULPI_DATA_1 pin mask */
+#define LDD_USB_ULPI_DATA_2_PIN 0x02000000u /*!< ULPI_DATA_2 pin mask */
+#define LDD_USB_ULPI_DATA_3_PIN 0x04000000u /*!< ULPI_DATA_3 pin mask */
+#define LDD_USB_ULPI_DATA_4_PIN 0x08000000u /*!< ULPI_DATA_4 pin mask */
+#define LDD_USB_ULPI_DATA_5_PIN 0x10000000u /*!< ULPI_DATA_5 pin mask */
+#define LDD_USB_ULPI_DATA_6_PIN 0x20000000u /*!< ULPI_DATA_6 pin mask */
+#define LDD_USB_ULPI_DATA_7_PIN 0x40000000u /*!< ULPI_DATA_7 pin mask */
+
+/* Alternate clock pin*/
+#define LDD_USB_CLKIN_PIN 0x80000000u /*!< Alternate clock pin mask */
+#define LDD_USB_ALT_CLK_PIN 0x80000000u /*!< Alternate clock pin mask */
+
+/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Cmd/CmdStatusPtr param. values */
+#define LDD_USB_CMD_GET_EP_STATUS 0x00u /*!< Get endpoint status command ID */
+#define LDD_USB_CMD_SET_EP_HALT_FATURE 0x01u /*!< Set endpoint HALT feature command ID */
+#define LDD_USB_CMD_CLR_EP_HALT_FATURE 0x02u /*!< Clear endpoint HALT feature command ID */
+
+#define LDD_USB_CMD_EP_STATUS_HALT_MASK 0x01u /*!< Endpoint halt status mask */
+
+
+/* DeviceSetUsbStatus()/DeviceGetUsbStatus methods Recipient param. values */
+/* (see USB 2.0, chapter 9.3.4 wIndex description)*/
+#define LDD_USB_ID_EP0_OUT 0x00u /*!< EP0 OUT component ID */
+#define LDD_USB_ID_EP0_IN 0x80u /*!< EP0 IN component ID */
+#define LDD_USB_ID_EP1_OUT 0x01u /*!< EP1 OUT component ID */
+#define LDD_USB_ID_EP1_IN 0x81u /*!< EP1 IN component ID */
+#define LDD_USB_ID_EP2_OUT 0x02u /*!< EP2 OUT component ID */
+#define LDD_USB_ID_EP2_IN 0x82u /*!< EP2 IN component ID */
+#define LDD_USB_ID_EP3_OUT 0x03u /*!< EP3 OUT component ID */
+#define LDD_USB_ID_EP3_IN 0x83u /*!< EP3 IN component ID */
+#define LDD_USB_ID_EP4_OUT 0x04u /*!< EP4 OUT component ID */
+#define LDD_USB_ID_EP4_IN 0x84u /*!< EP4 IN component ID */
+#define LDD_USB_ID_EP5_OUT 0x05u /*!< EP5 OUT component ID */
+#define LDD_USB_ID_EP5_IN 0x85u /*!< EP5 IN component ID */
+#define LDD_USB_ID_EP6_OUT 0x06u /*!< EP6 OUT component ID */
+#define LDD_USB_ID_EP6_IN 0x86u /*!< EP6 IN component ID */
+#define LDD_USB_ID_EP7_OUT 0x07u /*!< EP7 OUT component ID */
+#define LDD_USB_ID_EP7_IN 0x87u /*!< EP7 IN component ID */
+#define LDD_USB_ID_EP8_OUT 0x08u /*!< EP8 OUT component ID */
+#define LDD_USB_ID_EP8_IN 0x88u /*!< EP8 IN component ID */
+#define LDD_USB_ID_EP9_OUT 0x09u /*!< EP9 OUT component ID */
+#define LDD_USB_ID_EP9_IN 0x89u /*!< EP9 IN component ID */
+#define LDD_USB_ID_EP10_OUT 0x0Au /*!< EP10 OUT component ID */
+#define LDD_USB_ID_EP10_IN 0x8Au /*!< EP10 IN component ID */
+#define LDD_USB_ID_EP11_OUT 0x0Bu /*!< EP11 OUT component ID */
+#define LDD_USB_ID_EP11_IN 0x8Bu /*!< EP11 IN component ID */
+#define LDD_USB_ID_EP12_OUT 0x0Cu /*!< EP12 OUT component ID */
+#define LDD_USB_ID_EP12_IN 0x8Cu /*!< EP12 IN component ID */
+#define LDD_USB_ID_EP13_OUT 0x0Du /*!< EP13 OUT component ID */
+#define LDD_USB_ID_EP13_IN 0x8Du /*!< EP13 IN component ID */
+#define LDD_USB_ID_EP14_OUT 0x0Eu /*!< EP14 OUT component ID */
+#define LDD_USB_ID_EP14_IN 0x8Eu /*!< EP14 IN component ID */
+#define LDD_USB_ID_EP15_OUT 0x0Fu /*!< EP15 OUT component ID */
+#define LDD_USB_ID_EP15_IN 0x8Fu /*!< EP15 IN component ID */
+#define LDD_USB_ID_EP_MASK 0x8Fu /*!< EP15 IN component ID */
+
+/* Token PID */
+#define LDD_USB_PID_OUT 0x01u /*!< OUT */
+#define LDD_USB_PID_IN 0x09u /*!< IN */
+#define LDD_USB_PID_SOF 0x05u /*!< SOF */
+#define LDD_USB_PID_SETUP 0x0Du /*!< SETUP */
+/* Data PID */
+#define LDD_USB_PID_DATA0 0x03u /*!< DATA0 */
+#define LDD_USB_PID_DATA1 0x0Bu /*!< DATA1 */
+#define LDD_USB_PID_DATA2 0x07u /*!< DATA2 */
+#define LDD_USB_PID_MDATA 0x0Fu /*!< MDATA */
+/* Handshake PID */
+#define LDD_USB_PID_ACK 0x02u /*!< ACK */
+#define LDD_USB_PID_NACK 0x0Au /*!< NACK */
+#define LDD_USB_PID_STALL 0x0Eu /*!< STALL */
+#define LDD_USB_PID_NYET 0x06u /*!< NYET */
+/* Special PID */
+#define LDD_USB_PID_PRE 0x0Cu /*!< PRE */
+#define LDD_USB_PID_ERR 0x0Cu /*!< ERR */
+#define LDD_USB_PID_SPLIT 0x08u /*!< SPLIT */
+#define LDD_USB_PID_PING 0x04u /*!< PING */
+
+/* Data direction */
+#define LDD_USB_DIR_OUT 0x00u /*!< Recipient is Device */
+#define LDD_USB_DIR_IN 0x80u /*!< Recipient is Host */
+#define LDD_USB_DIR_MASK 0x80u /*!< Bit mask for data transfer direction */
+
+/* Flags used in the TD.Head.Flags variable */
+
+/* The following flag can be used to force zero-length termination(ZLT) of the transfer.
+ Note: ZLT can be set for all transfer during the initialization of the endpoint.
+*/
+#define LDD_USB_DEVICE_TRANSFER_FLAG_ZLT 0x01u
+
+/* If the TRANSFER_FLAG_EXT_PARAM is defined all variables of the TD are used
+ and TD must NOT be freed until transfer is done or is cancelled
+ (TransferState != LDD_USB_TRANSFER_PENDING)
+ If not defined only the Head member of TD is used and TD can be freed after
+ Send/Recv() method returns.
+*/
+#define LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM 0x02u
+
+
+#define ERR_COMPONET_SPECIFIC 0x100u
+
+/* Device mode USB specific error codes */
+#define ERR_USB_DEVICE_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Device mode is disabled (by the user or by the clock configuration) */
+#define ERR_USB_DEVICE_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Device mode is disabled by the OTG driver */
+#define ERR_USB_DEVICE_VBUS_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< No VBUS is detected */
+#define ERR_USB_DEVICE_VBUS_ON (ERR_COMPONET_SPECIFIC + 0x03u) /*!< VBUS is detected */
+#define ERR_USB_DEVICE_ENABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is enabled */
+#define ERR_USB_DEVICE_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Device is suspended */
+#define ERR_USB_DEVICE_SUSPENDED_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Device is suspended and ready to generate resume signaling */
+#define ERR_USB_DEVICE_RESUME_PENDING (ERR_COMPONET_SPECIFIC + 0x07u) /*!< Device generates resume signaling */
+
+/* Host mode USB specific error codes */
+#define ERR_USB_HOST_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< Host mode is disabled (by the user or by the clock configuration) */
+#define ERR_USB_HOST_DISABLED_BY_OTG (ERR_COMPONET_SPECIFIC + 0x01u) /*!< Host mode is disabled by the OTG driver */
+#define ERR_USB_HOST_PORT_POWERED_OFF (ERR_COMPONET_SPECIFIC + 0x02u) /*!< Port is power off */
+#define ERR_USB_HOST_PORT_DISCONNECTED (ERR_COMPONET_SPECIFIC + 0x03u) /*!< Port is power on */
+#define ERR_USB_HOST_PORT_DISABLED (ERR_COMPONET_SPECIFIC + 0x04u) /*!< Device is connected to the port */
+#define ERR_USB_HOST_PORT_RESETING (ERR_COMPONET_SPECIFIC + 0x05u) /*!< Port generates reset signaling */
+#define ERR_USB_HOST_PORT_RESET_RECOVERING (ERR_COMPONET_SPECIFIC + 0x06u) /*!< Port waits 10ms for reset recovery */
+#define ERR_USB_HOST_PORT_ENABLED (ERR_COMPONET_SPECIFIC + 0x07u) /*!< PortDevice is connected, reset and ready to use */
+#define ERR_USB_HOST_PORT_SUSPENDED (ERR_COMPONET_SPECIFIC + 0x08u) /*!< Port is suspended */
+#define ERR_USB_HOST_PORT_RESUME_READY (ERR_COMPONET_SPECIFIC + 0x09u) /*!< Port can generate resume signaling */
+#define ERR_USB_HOST_PORT_RESUMING (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< Port generates resume signaling */
+#define ERR_USB_HOST_PORT_RESUME_RECOVERING (ERR_COMPONET_SPECIFIC + 0x0Bu) /*!< Port generates resume signaling */
+
+/* OTG mode USB specific error codes */
+#define ERR_USB_OTG_DISABLED (ERR_COMPONET_SPECIFIC + 0x00u) /*!< OTG device is DISABLED state */
+#define ERR_USB_OTG_ENABLED_PENDING (ERR_COMPONET_SPECIFIC + 0x01u) /*!< OTG device is in ENABLED_PENDING state */
+#define ERR_USB_OTG_A_IDLE (ERR_COMPONET_SPECIFIC + 0x02u) /*!< OTG device is in A_IDLE state */
+#define ERR_USB_OTG_A_WAIT_VRISE (ERR_COMPONET_SPECIFIC + 0x03u) /*!< OTG device is in WAIT_VRISE state */
+#define ERR_USB_OTG_A_WAIT_VFALL (ERR_COMPONET_SPECIFIC + 0x05u) /*!< OTG device is in A_WAIT_VFALL state */
+#define ERR_USB_OTG_A_WAIT_BCON (ERR_COMPONET_SPECIFIC + 0x07u) /*!< OTG device is in A_WAIT_BCON state */
+#define ERR_USB_OTG_A_VBUS_ERROR (ERR_COMPONET_SPECIFIC + 0x09u) /*!< OTG device is in A_VBUS_ERROR state */
+#define ERR_USB_OTG_A_SUSPEND (ERR_COMPONET_SPECIFIC + 0x0Au) /*!< OTG device is in A_SUSPEND state */
+
+#define ERR_USB_OTG_B_IDLE (ERR_COMPONET_SPECIFIC + 0x0Cu) /*!< OTG device is in B_IDLE state */
+#define ERR_USB_OTG_B_SRP_INIT (ERR_COMPONET_SPECIFIC + 0x0Eu) /*!< OTG device is in B_SRP_INIT state */
+#define ERR_USB_OTG_B_WAIT_ACON (ERR_COMPONET_SPECIFIC + 0x0Fu) /*!< OTG device is in B_WAIT_ACON state */
+
+#define ERR_USB_OTG_A_HOST (ERR_COMPONET_SPECIFIC + 0x10u) /*!< OTG device is in A_HOST state */
+#define ERR_USB_OTG_A_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x11u) /*!< OTG device is in A_PERIPHERAL state */
+#define ERR_USB_OTG_B_HOST (ERR_COMPONET_SPECIFIC + 0x12u) /*!< OTG device is in B_HOST state */
+#define ERR_USB_OTG_B_PERIPHERAL (ERR_COMPONET_SPECIFIC + 0x13u) /*!< OTG device is in B_PERIPHERAL state */
+
+/*! Device speed symbolic names */
+typedef enum {
+ LDD_USB_LOW_SPEED = 0x00u, /*!< Low-speed - 6 Mb/s mode */
+ LDD_USB_FULL_SPEED = 0x01u, /*!< Full-speed - 12 Mb/s mode */
+ LDD_USB_HIGH_SPEED = 0x02u, /*!< High-speed - 480 Mb/s mode */
+ LDD_USB_SPEED_UNKNOWN = 0xFFu /*!< Unkown speed mode */
+} LDD_USB_TBusSpeed;
+
+/*! Transfer type symbolic names */
+typedef enum {
+ LDD_USB_CONTROL = 0x00u, /*!< Conrol transfer type */
+ LDD_USB_ISOCHRONOUS = 0x01u, /*!< Isochronous transfer type */
+ LDD_USB_BULK = 0x02u, /*!< Bulk transfer type */
+ LDD_USB_INTERRUPT = 0x03u /*!< Interrupt transfer type */
+} LDD_USB_TTransferType;
+
+/*! Transfer state symbolic names */
+typedef enum {
+ LDD_USB_TRANSFER_NONE = 0x00u, /*!< Default valeu for new TD */
+ LDD_USB_TRANSFER_DONE = 0x01u, /*!< Transfer done */
+ LDD_USB_TRANSFER_ERROR_CANCELLED = 0x02u, /*!< Transfer cancelled by the user */
+ LDD_USB_TRANSFER_ERROR_STALLED = 0x03u, /*!< Transfer stalled */
+ LDD_USB_TRANSFER_ERROR_BUS_TIMEOUT = 0x04u, /*!< Bus timeute detected */
+ LDD_USB_TRANSFER_ERROR_DATA = 0x05u, /*!< Data error deteceted */
+ LDD_USB_TRANSFER_ERROR_PID = 0x06u, /*!< PID error deteceted */
+ LDD_USB_TRANSFER_ERROR_EOF = 0x07u, /*!< EOF error deteceted */
+ LDD_USB_TRANSFER_ERROR_CRC16 = 0x08u, /*!< CRC16 error deteceted */
+ LDD_USB_TRANSFER_ERROR_DFN8 = 0x09u, /*!< DFN8 error deteceted */
+ LDD_USB_TRANSFER_ERROR_DMA = 0x0Au, /*!< DMA error deteceted */
+ LDD_USB_TRANSFER_ERROR_BTS = 0x0Bu, /*!< BTS error deteceted */
+ LDD_USB_TRANSFER_ERROR = 0x0Fu, /*!< Transfer error deteceted */
+ LDD_USB_TRANSFER_QUEUED = 0x10u, /*!< Transfer queued */
+ LDD_USB_TRANSFER_PENDING = 0x30u /*!< Transfer in proggress */
+} LDD_USB_TTransferState;
+
+/*! Setup data packet structure, uint16_t items must be in little-endian format */
+typedef struct LDD_USB_TSDP_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request code */
+ uint16_t wValue; /*!< Word-sized field that varies according to request */
+ uint16_t wIndex; /*!< Word-sized field that varies according to request, typically used to pass an index or offset */
+ uint16_t wLength; /*!< Number of bytes to transfer if there is a data stage */
+} LDD_USB_TSDP;
+
+/*! Endpoint descriptor structure, uint16_t items must be in little-endian format */
+typedef struct LDD_USB_TEpDescriptor_Struct {
+ uint8_t bLength; /*!< Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint8_t bEndpointAddress; /*!< Endpoint address */
+ uint8_t bmAttributes; /*!< Endpoint attributes */
+ uint16_t wMaxPacketSize; /*!< Maximum packet size the endpoint is capable of sending or receiving */
+ uint8_t bInterval; /*!< Interval for polling endpoint for data transfers */
+} LDD_USB_TEpDescriptor;
+
+/*! Standard device descriptor structure, uint16_t items must be in little-endian format */
+typedef struct LDD_USB_TDevDescriptor_Struct {
+ uint8_t bLength; /*!< Size of this descriptor in bytes */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint16_t bcdUSB; /*!< USB specification release number in binary-coded Decimal */
+ uint8_t bDeviceClass; /*!< Class code (assigned by the USB-IF) */
+ uint8_t bDeviceSubClass; /*!< Subclass code (assigned by the USB-IF) */
+ uint8_t bDeviceProtocol; /*!< Protocol code (assigned by the USB-IF) */
+ uint8_t bMaxPacketSize0; /*!< Maximum packet size for endpoint zero */
+ uint16_t idVendor; /*!< Vendor ID (assigned by the USB-IF) */
+ uint16_t idProduct; /*!< Product ID (assigned by the manufacturer) */
+ uint16_t bcdDevice; /*!< Device release number in binary-coded decimal */
+ uint8_t iManufacturer; /*!< Index of string descriptor describing manufacturer */
+ uint8_t iProduct; /*!< Index of string descriptor describing product */
+ uint8_t iSerialNumber; /*!< Index of string descriptor describing the device’s serial number */
+ uint8_t bNumConfigurations; /*!< Number of possible configurations */
+} LDD_USB_TDevDescriptor;
+
+
+/*! Device transfer descriptor structure forward declaration */
+struct LDD_USB_Device_TTD_Struct;
+
+/*! Device transfer done callback prototype */
+typedef void (LDD_USB_Device_TTransferDoneCalback)(LDD_TDeviceData *DevDataPtr, struct LDD_USB_Device_TTD_Struct *TrParamPtr);
+
+/*! Device transfer descriptor structure - head part */
+typedef struct LDD_USB_Device_TTD_Head_Struct {
+ uint8_t EpNum; /*!< Endpoint number */
+ LDD_TData *BufferPtr; /*!< Buffer address */
+ uint16_t BufferSize; /*!< Buffer size */
+ uint8_t Flags; /*!< Transfer flags - see constants definition */
+} LDD_USB_Device_TTD_Head;
+
+/*! Device transfer descriptor structure */
+typedef struct LDD_USB_Device_TTD_Struct {
+ /* Requierd variables */
+ LDD_USB_Device_TTD_Head Head; /*!< Td head data, not changed by the driver */
+ /* Optional items - the following items are used */
+ /* only if Head.Flags & LDD_USB_DEVICE_TRANSFER_FLAG_EXT_PARAM != 0 */
+ LDD_USB_TTransferState TransferState; /*!< Transfer state. Set by the driver */
+ uint16_t TransmittedDataSize; /*!< Transmitted data size. Set by the driver */
+ LDD_USB_Device_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */
+ uint8_t *ParamPtr; /*!< User parameter. Not changed by the driver */
+} LDD_USB_Device_TTD;
+
+/*! USB device states symbolic names */
+typedef enum {
+ LDD_USB_DEVICE_DISABLED = ERR_USB_DEVICE_DISABLED, /*!< Device mode is disabled (by the user or by the clock configuration) */
+ LDD_USB_DEVICE_DISABLED_BY_OTG = ERR_USB_DEVICE_DISABLED_BY_OTG, /*!< Device mode is disabled by the OTG driver */
+ LDD_USB_DEVICE_VBUS_OFF = ERR_USB_DEVICE_VBUS_OFF, /*!< No VBUS is detected */
+ LDD_USB_DEVICE_VBUS_ON = ERR_USB_DEVICE_VBUS_ON, /*!< VBUS is detected */
+ LDD_USB_DEVICE_ENABLED = ERR_USB_DEVICE_ENABLED, /*!< Device is enabled - reset by the host */
+ LDD_USB_DEVICE_SUSPENDED = ERR_USB_DEVICE_SUSPENDED, /*!< Device is suspended - Bus is idle more then 3 ms */
+ LDD_USB_DEVICE_SUSPENDED_RESUME_READY = ERR_USB_DEVICE_SUSPENDED_RESUME_READY, /*!< Device can generate resume signaling - Bus is idle more then 5 ms. */
+ LDD_USB_DEVICE_RESUME_PENDING = ERR_USB_DEVICE_RESUME_PENDING /*!< Device generates resume signaling */
+} LDD_USB_Device_TState;
+
+/*! USB host mode states symbolic names */
+typedef enum {
+ LDD_USB_HOST_DISABLED = ERR_USB_HOST_DISABLED, /*!< Host mode is disabled (by the user or by the clock configuration) */
+ LDD_USB_HOST_DISABLED_BY_OTG = ERR_USB_HOST_DISABLED_BY_OTG, /*!< Host mode is disabled by the OTG driver */
+ LDD_USB_HOST_PORT_POWERED_OFF = ERR_USB_HOST_PORT_POWERED_OFF, /*!< Port is powered-off */
+ LDD_USB_HOST_PORT_DISCONNECTED = ERR_USB_HOST_PORT_DISCONNECTED, /*!< No device is connected */
+ LDD_USB_HOST_PORT_DISABLED = ERR_USB_HOST_PORT_DISABLED, /*!< Device is connected to the port */
+ LDD_USB_HOST_PORT_RESETING = ERR_USB_HOST_PORT_RESETING, /*!< Port generates reset signaling */
+ LDD_USB_HOST_PORT_RESET_RECOVERING = ERR_USB_HOST_PORT_RESET_RECOVERING, /*!< Port waits 10 ms for reset recovery */
+ LDD_USB_HOST_PORT_ENABLED = ERR_USB_HOST_PORT_ENABLED, /*!< Device is connected, reset and ready to use */
+ LDD_USB_HOST_PORT_SUSPENDED = ERR_USB_HOST_PORT_SUSPENDED, /*!< Port is suspended */
+ LDD_USB_HOST_PORT_RESUME_READY = ERR_USB_HOST_PORT_RESUME_READY, /*!< Port is ready to generate resume signaling */
+ LDD_USB_HOST_PORT_RESUMING = ERR_USB_HOST_PORT_RESUMING, /*!< Port generates resume signaling */
+ LDD_USB_HOST_PORT_RESUME_RECOVERING = ERR_USB_HOST_PORT_RESUME_RECOVERING /*!< Port waits 10 ms for resume recovery */
+} LDD_USB_Host_TState;
+
+/*! USB otg mode states symbolic names */
+typedef enum {
+ LDD_USB_OTG_DISABLED = ERR_USB_OTG_DISABLED, /*!< OTG device is in DISABLED state */
+ LDD_USB_OTG_ENABLED = ERR_USB_OTG_ENABLED_PENDING, /*!< OTG device is in ENABLED_PENDING state */
+ LDD_USB_OTG_A_IDLE = ERR_USB_OTG_A_IDLE, /*!< OTG device is in A_IDLE state */
+ LDD_USB_OTG_A_WAIT_VRISE = ERR_USB_OTG_A_WAIT_VRISE, /*!< OTG device is in A_WAIT_VRISE state */
+ LDD_USB_OTG_A_WAIT_VFALL = ERR_USB_OTG_A_WAIT_VFALL, /*!< OTG device is in A_WAIT_VFALL state */
+ LDD_USB_OTG_A_WAIT_BCON = ERR_USB_OTG_A_WAIT_BCON, /*!< OTG device is in A_WAIT_BCON state */
+ LDD_USB_OTG_A_VBUS_ERROR = ERR_USB_OTG_A_VBUS_ERROR, /*!< OTG device is in A_VBUS_ERROR state */
+ LDD_USB_OTG_A_SUSPEND = ERR_USB_OTG_A_SUSPEND, /*!< OTG device is in A_SUSPEND state */
+ LDD_USB_OTG_B_IDLE = ERR_USB_OTG_B_IDLE, /*!< OTG device is in B_IDLE state */
+ LDD_USB_OTG_B_SRP_INIT = ERR_USB_OTG_B_SRP_INIT, /*!< OTG device is in B_SRP_INIT state */
+ LDD_USB_OTG_B_WAIT_ACON = ERR_USB_OTG_B_WAIT_ACON, /*!< OTG device is in B_WAIT_ACON state */
+ LDD_USB_OTG_A_HOST = ERR_USB_OTG_A_HOST, /*!< OTG device is in A_HOST state */
+ LDD_USB_OTG_A_PERIPHERAL = ERR_USB_OTG_A_PERIPHERAL, /*!< OTG device is in A_PERIPHERAL state */
+ LDD_USB_OTG_B_HOST = ERR_USB_OTG_B_HOST, /*!< OTG device is in B_HOST state */
+ LDD_USB_OTG_B_PERIPHERAL = ERR_USB_OTG_B_PERIPHERAL /*!< OTG device is in B_PERIPHERAL state */
+} LDD_USB_Otg_TState;
+
+/*! USB Otg commands symbolic names */
+typedef enum {
+ LDD_USB_OTG_CMD_SET_A_BUS_REQUEST, /*!< A-device application wants to use the bus */
+ LDD_USB_OTG_CMD_CLR_A_BUS_REQUEST, /*!< A-device application doesn't want to use the bus */
+ LDD_USB_OTG_CMD_SET_B_BUS_REQUEST, /*!< B-device application wants to use the bus */
+ LDD_USB_OTG_CMD_CLR_B_BUS_REQUEST, /*!< B-device application doesn't want to use the bus */
+ LDD_USB_OTG_CMD_SET_A_BUS_DROP, /*!< A-device application needs to power down the bus */
+ LDD_USB_OTG_CMD_CLR_A_BUS_DROP, /*!< A-device application doesn't need to power down the bus */
+ LDD_USB_OTG_CMD_SET_A_SUSPEND_REQUEST, /*!< A-device application wants to suspend the bus */
+ LDD_USB_OTG_CMD_CLR_A_SUSPEND_REQUEST, /*!< A-device application doesn't want to suspend the bus */
+ LDD_USB_OTG_CMD_SET_A_SET_B_HNP_EN_REQUEST, /*!< A-device sets HNP enabled feature on B-device */
+ LDD_USB_OTG_CMD_CLR_A_SET_B_HNP_EN_REQUEST, /*!< A-device clears HNP enabled feature on B-device */
+ LDD_USB_OTG_CMD_SET_B_HNP_EN_REQUEST, /*!< Enable B-device HNP */
+ LDD_USB_OTG_CMD_CLR_B_HNP_EN_REQUEST /*!< Disable B-device HNP */
+} LDD_USB_Otg_TCmd;
+
+/*! USB host port control commands symbolic names */
+typedef enum {
+ LDD_USB_HOST_PORT_CMD_POWER_ON, /*!< Power-on the bus */
+ LDD_USB_HOST_PORT_CMD_POWER_OFF, /*!< Power-off the bus */
+ LDD_USB_HOST_PORT_CMD_RESET, /*!< Perform the bus reset signaling and call event after the reset recovery interval elapse */
+ LDD_USB_HOST_PORT_CMD_RESUME, /*!< Perform the bus resume signaling and call event after the resume recovery interval elapse */
+ LDD_USB_HOST_PORT_CMD_SUSPEND, /*!< Suspend the bus and transceiver */
+ LDD_USB_HOST_PORT_CMD_DISABLE /*!< Disable the port */
+} LDD_USB_Host_TPortControlCmd;
+
+/*! USB host handle prototypes */
+typedef void LDD_USB_Host_TPipeHandle; /*!< Pipe handle prototype */
+typedef void LDD_USB_Host_TTransferHandle; /*!< Transfer handle prototype */
+
+/*! USB host pipe descriptor structure */
+typedef struct LDD_USB_Host_TPipeDescr_Struct {
+ uint8_t DevAddress; /*!< Device address */
+ LDD_USB_TBusSpeed DevSpeed; /*!< Device speed */
+ uint8_t EpNumber; /*!< EP number */
+ uint8_t EpDir; /*!< EP direction */
+ LDD_USB_TTransferType TransferType; /*!< EP Transfer type */
+ uint16_t MaxPacketSize; /*!< EP max. packet size */
+ uint8_t TrPerUFrame; /*!< Transaction pre microframe */
+ uint32_t Interval; /*!< Interval for polling endpoint for data transfers */
+ uint32_t NAKCount; /*!< NAK count */
+ uint8_t Flags; /*!< 1 = ZLT */
+} LDD_USB_Host_TPipeDescr;
+
+/*! USB host transfer done callback prototype */
+typedef void (LDD_USB_Host_TTransferDoneCalback)(
+ LDD_TDeviceData *DevDataPtr, /*!< User value passed as parameter of the Init() method */
+ LDD_TData *BufferPtr, /*!< Buffer address */
+ uint16_t BufferSize, /*!< Transferred data size */
+ uint8_t *ParamPtr, /*!< User value passed in Send()/Recv() method */
+ LDD_USB_TTransferState Status /*!< Transfer status */
+);
+
+/*! USB host transfer descriptor structure */
+typedef struct LDD_USB_Host_TTD_Struct {
+ LDD_TData *BufferPtr; /*!< Buffer address */
+ uint16_t BufferSize; /*!< Buffer size */
+ uint8_t Flags; /*!< Transfer flags */
+ LDD_USB_Host_TTransferDoneCalback *CallbackFnPtr; /*!< Address of the callback function. Must be set by the caller */
+ uint8_t *ParamPtr; /*!< User parameter. Not changed by the driver */
+ LDD_USB_TSDP *SDPPrt; /*!< Setup data buffer pointer */
+} LDD_USB_Host_TTD;
+
+/*! Following USB constants and types are for test purpose only */
+
+/* Request types */
+#define LDD_USB_REQ_TYPE_STANDARD 0x00u /*!< Standard request */
+#define LDD_USB_REQ_TYPE_CLASS 0x20u /*!< Class request */
+#define LDD_USB_REQ_TYPE_VENDOR 0x40u /*!< Vendor request */
+#define LDD_USB_REQ_TYPE_MASK 0x60u /*!< Bit mask for request type (bmRequestType) */
+
+/* Request recepient */
+#define LDD_USB_REQ_RECP_DEVICE 0x00u /*!< Recipient = Device */
+#define LDD_USB_REQ_RECP_INTERFACE 0x01u /*!< Recipient = Interface */
+#define LDD_USB_REQ_RECP_ENDPOINT 0x02u /*!< Recipient = Endpoint */
+#define LDD_USB_REQ_RECP_OTHER 0x03u /*!< Recipient = Other */
+#define LDD_USB_REQ_RECP_MASK 0x03u /*!< Bit mask for recipient */
+
+/* Standard request codes (bRequest) */
+#define LDD_USB_REQ_GET_STATUS 0x00u /*!< GET_STATUS request code */
+#define LDD_USB_REQ_CLEAR_FEATURE 0x01u /*!< CLEAR_FEATURE request code */
+#define LDD_USB_REQ_SET_FEATURE 0x03u /*!< SET_FEATURE request code */
+#define LDD_USB_REQ_GET_STATE 0x04u /*!< GET_STATE request code (for Hub Class only)*/
+#define LDD_USB_REQ_SET_ADDRESS 0x05u /*!< SET_ADDRESS request code */
+#define LDD_USB_REQ_GET_DESCRIPTOR 0x06u /*!< GET_DESCRIPTOR request code */
+#define LDD_USB_REQ_SET_DESCRIPTOR 0x07u /*!< SET_DESCRIPTOR request code, this request is not supported */
+#define LDD_USB_REQ_GET_CONFIGURATION 0x08u /*!< GET_CONFIGURATION request code */
+#define LDD_USB_REQ_SET_CONFIGURATION 0x09u /*!< SET_CONFIGURATION request code */
+#define LDD_USB_REQ_GET_INTERFACE 0x0Au /*!< GET_INTERFACE request code */
+#define LDD_USB_REQ_SET_INTERFACE 0x0Bu /*!< SET_INTERFACE request code */
+#define LDD_USB_REQ_SYNCH_FRAME 0x0Cu /*!< SYNCH_FRAME request code */
+
+/* Standard request words for device (bmRequestType | bRequest) */
+#define LDD_USB_STD_REQ_GET_DEV_STATUS 0x0080u /*!< GET_DEVICE_STATUS bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_CLR_DEV_FEATURE 0x0100u /*!< CLEAR_DEVICE_FEATURE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_DEV_FEATURE 0x0300u /*!< SET_DEVICE_FEATURE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_ADDRESS 0x0500u /*!< SET_DEVICE_ADDRESS bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_GET_DESCRIPTOR 0x0680u /*!< GET_DESCRIPTOR bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_DESCRIPTOR 0x0700u /*!< SET_DESCRIPTOR bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_GET_CONFIGURATION 0x0880u /*!< GET_DEVICE_CONFIGURATION bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_CONFIGURATION 0x0900u /*!< SET_DEVICE_CONFIGURATION bmRequestType and bRequest word */
+
+/* Standard request words for interface (bmRequestType | bRequest) */
+#define LDD_USB_STD_REQ_GET_INT_STATUS 0x0081u /*!< GET_INTERFACE_STATUS bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_CLR_INT_FEATURE 0x0101u /*!< CLEAR_INTERFACE_FEATURE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_INT_FEATURE 0x0301u /*!< SET_INTERFACE_FEATURE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_GET_INTERFACE 0x0A81u /*!< GET_DEVICE_INTERFACE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_INTERFACE 0x0B01u /*!< SET_DEVICE_INTERFACE bmRequestType and bRequest word */
+
+/* Standard request words for endpoint (bmRequestType | bRequest) */
+#define LDD_USB_STD_REQ_GET_EP_STATUS 0x0082u /*!< GET_ENDPOINT_STATUS bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_CLR_EP_FEATURE 0x0102u /*!< CLEAR_ENDPOINT_FEATURE bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SET_EP_FEATURE 0x0302u /*!< ENDPOINT_ bmRequestType and bRequest word */
+#define LDD_USB_STD_REQ_SYNCH_FRAME 0x0C12u /*!< SYNCH_DEVICE_FRAME bmRequestType and bRequest code */
+
+#define LDD_USB_STATUS_DEVICE_SELF_POWERED_MASK 0x01u
+#define LDD_USB_STATUS_DEVICE_REMOTE_WAKEUP_MASK 0x02u
+
+/* Standard descriptors */
+#define LDD_USB_DT_DEVICE 0x01u /*!< Device descriptor */
+#define LDD_USB_DT_CONFIGURATION 0x02u /*!< Configuration descriptor */
+#define LDD_USB_DT_STRING 0x03u /*!< String descriptor */
+#define LDD_USB_DT_INTERFACE 0x04u /*!< Interface descriptor */
+#define LDD_USB_DT_ENDPOINT 0x05u /*!< Endpoint descriptor */
+#define LDD_USB_DT_DEVICE_QUALIFIER 0x06u /*!< Device qualifier descriptor */
+#define LDD_USB_DT_OTHER_SPEED_CONFIGURATION 0x07u /*!< Other speed configuration descriptor */
+#define LDD_USB_DT_INTERFACE_POWER 0x08u /*!< Interface-level power management descriptor */
+#define LDD_USB_DT_OTG 0x09u /*!< OTG descriptor */
+#define LDD_USB_DT_DEBUG 0x0Au /*!< Debug descriptor */
+#define LDD_USB_DT_INTERFACE_ASSOCIATION 0x0Bu /*!< Interface association descriptor */
+
+/* Standard feature selectors */
+#define LDD_USB_FEATURE_EP_HALT 0x00u /*!< Endpoint HALT feature selector */
+#define LDD_USB_FEATURE_DEV_REMOTE_WAKEUP 0x01u /*!< Remote Wake-up feature selector */
+#define LDD_USB_FEATURE_DEV_TEST_MODE 0x02u /*!< Test mode feature selector */
+
+/*! Get decriptor request structure */
+typedef struct LDD_USB_TGetDecriptorRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint8_t bDescriptorIndex; /*!< Descriptor index */
+ uint8_t bDescriptorType; /*!< Descriptor type */
+ uint16_t wLanguageID; /*!< Language ID */
+ uint16_t wLength; /*!< Requested data size */
+} LDD_USB_TGetDecriptorRequest;
+
+/*! Get endpoint status request structure */
+typedef struct LDD_USB_TEndpointStatusRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wValue; /*!< Not used, should be set to zero */
+ uint8_t bEndpoint; /*!< Endpoint address */
+ uint8_t bIndexHigh; /*!< Not used, should be set to zero */
+ uint16_t wLength; /*!< Reqested data size, should be set to 2 */
+} LDD_USB_TEndpointStatusRequest;
+
+/*! Clear/Set endpoint feature request structure */
+typedef struct LDD_USB_TEndpointFeatureRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wFeatureSelector; /*!< Feature selector */
+ uint8_t bEndpoint; /*!< Endpoint address */
+ uint8_t bIndexHigh; /*!< Not used, should be set to zero */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TEndpointFeatureRequest;
+
+/*! Clear/Set interface request structure */
+typedef struct LDD_USB_TInterfaceFeatureRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wFeatureSelector; /*!< Feature selector */
+ uint16_t wInterface; /*!< Interface index */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TInterfaceFeatureRequest;
+
+/*! Clear/Set device request structure */
+typedef struct LDD_USB_TDeviceFeatureRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wFeatureSelector; /*!< Feature selector */
+ uint16_t wIndex; /*!< Not used, should be set to zero */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TDeviceFeatureRequest;
+
+/*! Get interface request structure */
+typedef struct LDD_USB_TGetInterfaceRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wWalue; /*!< Not used, should be zero */
+ uint16_t wInterface; /*!< Interface index */
+ uint16_t wLength; /*!< Reqested data size, should be set to 1 */
+} LDD_USB_TGetInterfaceRequest;
+
+/*! Set interface request structure */
+typedef struct LDD_USB_TSetInterfaceRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint16_t wAltSet; /*!< Alternate setting */
+ uint16_t wInterface; /*!< Interface index */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TSetInterfaceRequest;
+
+/*! Set address request structure */
+typedef struct LDD_USB_TSetAddressRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint8_t DeviceAddress; /*!< Device address */
+ uint8_t bValueHigh; /*!< Not used, should be set to zero */
+ uint16_t wIndex; /*!< Not used, should be set to zero */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TSetAddressRequest;
+
+/*! Set address request structure */
+typedef struct LDD_USB_TSetConfigRequest_Struct {
+ uint8_t bmRequestType; /*!< Characteristics of request */
+ uint8_t bRequest; /*!< Request ID */
+ uint8_t bValueHigh; /*!< Not used, should be set to zero */
+ uint8_t ConfigNumber; /*!< Configuration number */
+ uint16_t wIndex; /*!< Not used, should be set to zero */
+ uint16_t wLength; /*!< Not used, should be set to zero */
+} LDD_USB_TSetConfigRequest;
+
+/*
+** ===================================================================
+** DAC device types and constants
+** ===================================================================
+*/
+#define LDD_DAC_OUTPUT_PIN_0 0x01u /*!< DAC output pin 0 mask */
+
+#define LDD_DAC_ON_BUFFER_END 0x01U /*!< OnBufferEnd event mask */
+#define LDD_DAC_ON_BUFFER_START 0x02U /*!< OnBufferStart event mask */
+#define LDD_DAC_ON_BUFFER_WATERMARK 0x04U /*!< OnBufferWatermark event mask */
+#define LDD_DAC_ON_COMPLETE LDD_DMA_ON_COMPLETE /*!< OnComplete event mask */
+#define LDD_DAC_ON_ERROR LDD_DMA_ON_ERROR /*!< OnError event mask */
+
+/*! Type specifying the DAC buffer work mode */
+typedef enum {
+ LDD_DAC_BUFFER_NORMAL_MODE = 0x00U, /*!< Normal (cyclic) mode */
+ LDD_DAC_BUFFER_SWING_MODE = 0x01U, /*!< Swing mode */
+ LDD_DAC_BUFFER_SCAN_MODE = 0x02U /*!< One-time scan mode */
+} LDD_DAC_TBufferMode;
+
+/*! Type specifying the DAC buffer watermark levels */
+typedef enum {
+ LDD_DAC_BUFFER_WATERMARK_L1 = 0x00U,
+ LDD_DAC_BUFFER_WATERMARK_L2 = 0x01U,
+ LDD_DAC_BUFFER_WATERMARK_L3 = 0x02U,
+ LDD_DAC_BUFFER_WATERMARK_L4 = 0x03U
+} LDD_DAC_TBufferWatermark;
+
+#define LDD_DAC_DMA_ERROR 0x01u /*!< DMA error mask */
+
+typedef void* LDD_DAC_TDataPtr; /*!< Type specifying the pointer to the DAC data variable */
+typedef uint32_t LDD_DAC_TData; /*!< The DAC data variable type */
+typedef uint32_t LDD_DAC_TErrorMask; /*!< Error mask */
+typedef uint32_t LDD_DAC_TArrayLength; /*!< Array length type */
+
+/*
+** ===================================================================
+** FLASH device types and constants
+** ===================================================================
+*/
+#define LDD_FLASH_ON_OPERATION_COMPLETE 0x02u /*!< OnOperationComplete event mask */
+#define LDD_FLASH_ON_ERROR 0x04u /*!< OnError event mask */
+
+#define LDD_FLASH_READ_COLLISION_ERROR 0x40u /*!< Read collision error flag's mask */
+#define LDD_FLASH_ACCESS_ERROR 0x20u /*!< Access error flag's mask */
+#define LDD_FLASH_PROTECTION_VIOLATION 0x10u /*!< Protection violation error flag's mask */
+#define LDD_FLASH_ERASE_VERIFICATION_ERROR 0x08u /*!< Erase verification error flag's mask */
+#define LDD_FLASH_MULTIPLE_WRITE_ERROR 0x04u /*!< Multiple write to one flash memory location error flag's mask */
+
+/*! Type specifying HW commands for a flash device */
+typedef enum {
+ LDD_FLASH_READ_1S_BLOCK = 0x00u, /*!< Checks if an entire program flash or data flash logical block has been erased to the specified margin level */
+ LDD_FLASH_READ_1S_SECTION = 0x01u, /*!< Checks if a section of program flash or data flash memory is erased to the specified read margin level */
+ LDD_FLASH_WRITE_BYTE = 0x04u, /*!< Program byte */
+ LDD_FLASH_WRITE_WORD = 0x05u, /*!< Program word */
+ LDD_FLASH_WRITE_LONG_WORD = 0x06u, /*!< Program long word */
+ LDD_FLASH_WRITE_PHRASE = 0x07u, /*!< Program phrase */
+ LDD_FLASH_ERASE_FLASH_BLOCK = 0x08u, /*!< Erase flash memory block */
+ LDD_FLASH_ERASE_SECTOR = 0x09u, /*!< Erase sector */
+ LDD_FLASH_ERASE_ALL_FLASH_BLOCKS = 0x44u /*!< Erase all flash memory blocks */
+} LDD_FLASH_TCommand;
+
+/*! Type specifying possible FLASH component operation types */
+typedef enum {
+ LDD_FLASH_NO_OPERATION, /*!< No operation - initial state */
+ LDD_FLASH_READ, /*!< Read operation */
+ LDD_FLASH_WRITE, /*!< Write operation */
+ LDD_FLASH_ERASE, /*!< Erase operation */
+ LDD_FLASH_ERASE_BLOCK, /*!< Erase block operation */
+ LDD_FLASH_VERIFY_ERASED_BLOCK /*!< Verify erased block operation */
+} LDD_FLASH_TOperationType;
+
+/*! Type specifying possible FLASH component operation states */
+typedef enum {
+ LDD_FLASH_FAILED = 0x00u, /*!< Operation has failed */
+ LDD_FLASH_STOP = 0x01u, /*!< The operation has been stopped */
+ LDD_FLASH_IDLE = 0x02u, /*!< No operation in progress */
+ LDD_FLASH_STOP_REQ = 0x03u, /*!< The operation is in the STOP request mode */
+ LDD_FLASH_START = 0x04u, /*!< Start of the operation, no operation steps have been done yet */
+ LDD_FLASH_RUNNING = 0x05u /*!< Operation is in progress */
+} LDD_FLASH_TOperationStatus;
+
+typedef uint8_t LDD_FLASH_TErrorFlags; /*!< Type specifying FLASH component's error flags bit field */
+
+typedef uint32_t LDD_FLASH_TAddress; /*!< Type specifying the Address parameter used by the FLASH component's methods */
+
+typedef uint32_t LDD_FLASH_TDataSize; /*!< Type specifying the Size parameter used by the FLASH component's methods */
+
+typedef uint16_t LDD_FLASH_TErasableUnitSize; /*!< Type specifying the Size output parameter of the GetErasableUnitSize method (pointer to a variable of this type is passed to the method) */
+
+/*! Type specifying the FLASH component's rrror status information */
+typedef struct {
+ LDD_FLASH_TOperationType CurrentOperation; /*!< Current operation */
+ LDD_FLASH_TCommand CurrentCommand; /*!< Last flash controller command */
+ LDD_FLASH_TErrorFlags CurrentErrorFlags; /*!< Bitfield with error flags. See FLASH2.h for details */
+ LDD_FLASH_TAddress CurrentAddress; /*!< Address of the flash memory location the error status is related to */
+ LDD_TData *CurrentDataPtr; /*!< Pointer to current input data the error status is related to */
+ LDD_FLASH_TDataSize CurrentDataSize; /*!< Size of the current input data to be programmed or erased in bytes */
+} LDD_FLASH_TErrorStatus;
+
+/*
+** ===================================================================
+** HSCMP device types and constants
+** ===================================================================
+*/
+
+#define LDD_ANALOGCOMP_ON_COMPARE 0x01u /*!< OnCompare event mask */
+
+/* Positive input pin masks */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_0_MASK 0x01U /*!< Mask for positive input pin 0 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_1_MASK 0x02U /*!< Mask for positive input pin 1 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_2_MASK 0x04U /*!< Mask for positive input pin 2 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_3_MASK 0x08U /*!< Mask for positive input pin 3 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_4_MASK 0x10U /*!< Mask for positive input pin 4 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_5_MASK 0x20U /*!< Mask for positive input pin 5 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_6_MASK 0x40U /*!< Mask for positive input pin 6 */
+#define LDD_ANALOGCOMP_POSITIVE_INPUT_7_MASK 0x80U /*!< Mask for positive input pin 7 */
+
+/* Negative input pin masks */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_0_MASK 0x0100U /*!< Mask for negative input pin 0 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_1_MASK 0x0200U /*!< Mask for negative input pin 1 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_2_MASK 0x0400U /*!< Mask for negative input pin 2 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_3_MASK 0x0800U /*!< Mask for negative input pin 3 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_4_MASK 0x1000U /*!< Mask for negative input pin 4 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_5_MASK 0x2000U /*!< Mask for negative input pin 5 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_6_MASK 0x4000U /*!< Mask for negative input pin 6 */
+#define LDD_ANALOGCOMP_NEGATIVE_INPUT_7_MASK 0x8000U /*!< Mask for negative input pin 7 */
+
+/* Output pin masks */
+#define LDD_ANALOGCOMP_OUTPUT_PIN_MASK 0x00010000U /*!< Mask for output pin */
+
+/* Window Sample pin masks */
+#define LDD_ANALOGCOMP_WINDOWSAMPLE_PIN_MASK 0x00020000UL
+
+/*! Type specifying comparator input number */
+typedef enum {
+ LDD_ANALOGCOMP_INPUT_0 = 0x00U, /*!< Analog input 0 selected */
+ LDD_ANALOGCOMP_INPUT_1 = 0x01U, /*!< Analog input 1 selected */
+ LDD_ANALOGCOMP_INPUT_2 = 0x02U, /*!< Analog input 2 selected */
+ LDD_ANALOGCOMP_INPUT_3 = 0x03U, /*!< Analog input 3 selected */
+ LDD_ANALOGCOMP_INPUT_4 = 0x04U, /*!< Analog input 4 selected */
+ LDD_ANALOGCOMP_INPUT_5 = 0x05U, /*!< Analog input 5 selected */
+ LDD_ANALOGCOMP_INPUT_6 = 0x06U, /*!< Analog input 6 selected */
+ LDD_ANALOGCOMP_INPUT_7 = 0x07U, /*!< Analog input 7 selected */
+ LDD_ANALOGCOMP_INPUT_DISABLED = 0x08U /*!< Analog input disabled */
+} LDD_AnalogComp_TComparatorInput;
+
+/*! Type specifying current comparator output status */
+typedef enum {
+ LDD_ANALOGCOMP_NO_EDGE = 0x00U, /*!< No edge detected on output */
+ LDD_ANALOGCOMP_FALLING_EDGE = 0x02U, /*!< Falling edge detected on output */
+ LDD_ANALOGCOMP_RISING_EDGE = 0x04U, /*!< Rising edge detected on output */
+ LDD_ANALOGCOMP_BOTH_EDGES = 0x06U /*!< Both edges detected on output */
+} LDD_AnalogComp_TCompareStatus;
+
+/*! Type specifying requested comparator mode */
+typedef enum {
+ LDD_ANALOGCOMP_RISING_EDGE_MODE = 0x10U, /*!< Rising edge detection */
+ LDD_ANALOGCOMP_FALLING_EDGE_MODE = 0x08U, /*!< Falling edge detection */
+ LDD_ANALOGCOMP_BOTH_EDGES_MODE = 0x18U /*!< Both edges detection */
+} LDD_AnalogComp_TComparatorMode;
+
+typedef uint8_t LDD_AnalogComp_TOutputValue; /*!< Type specifying comparator output value */
+
+/*
+** ===================================================================
+** SDHC component types and constants
+** ===================================================================
+*/
+
+#define LDD_SDHC_CARD_DATA_WIDTH_1_BIT 0x01u /*!< Card supports 1 bit data bus */
+#define LDD_SDHC_CARD_DATA_WIDTH_4_BIT 0x02u /*!< Card supports 4 bit data bus */
+#define LDD_SDHC_CARD_DATA_WIDTH_8_BIT 0x04u /*!< Card supports 8 bit data bus */
+#define LDD_SDHC_CARD_BLOCK_READ 0x01u /*!< Card supports block reading */
+#define LDD_SDHC_CARD_BLOCK_WRITE 0x04u /*!< Card supports block writing */
+#define LDD_SDHC_CARD_ERASE 0x08u /*!< Card supports block erasion */
+#define LDD_SDHC_CARD_WRITE_PROTECTION 0x10u /*!< Card supports write protection */
+#define LDD_SDHC_CARD_IO 0x80u /*!< Card supports IO */
+
+#define LDD_SDHC_CLK_PIN 0x01u /*!< SD clock pin mask */
+#define LDD_SDHC_CMD_PIN 0x02u /*!< SD command line pin mask */
+#define LDD_SDHC_DAT0_PIN 0x04u /*!< SD data line 0 pin mask */
+#define LDD_SDHC_DAT1_PIN 0x08u /*!< SD data line 1 pin mask */
+#define LDD_SDHC_DAT2_PIN 0x10u /*!< SD data line 2 pin mask */
+#define LDD_SDHC_DAT3_PIN 0x20u /*!< SD data line 3 pin mask */
+#define LDD_SDHC_DAT4_PIN 0x40u /*!< SD data line 4 pin mask */
+#define LDD_SDHC_DAT5_PIN 0x80u /*!< SD data line 5 pin mask */
+#define LDD_SDHC_DAT6_PIN 0x0100u /*!< SD data line 6 pin mask */
+#define LDD_SDHC_DAT7_PIN 0x0200u /*!< SD data line 7 pin mask */
+#define LDD_SDHC_CD_PIN 0x0400u /*!< SD card detection pin mask */
+#define LDD_SDHC_WP_PIN 0x0800u /*!< SD write protection pin mask */
+#define LDD_SDHC_LCTL_PIN 0x1000u /*!< SD LED control pin mask */
+#define LDD_SDHC_VS_PIN 0x2000u /*!< SD voltage control pin mask */
+
+#define LDD_SDHC_ON_CARD_INSERTED 0x01u /*!< OnCardInserted event mask */
+#define LDD_SDHC_ON_CARD_REMOVED 0x02u /*!< OnCardRemoved event mask */
+#define LDD_SDHC_ON_FINISHED 0x04u /*!< OnFinished event mask */
+
+/*! Card types */
+typedef enum {
+ LDD_SDHC_SD, /*!< Secure Digital memory card */
+ LDD_SDHC_SDIO, /*!< Secure Digital IO card */
+ LDD_SDHC_SDCOMBO, /*!< Combined Secure Digital memory and IO card */
+ LDD_SDHC_MMC, /*!< MultiMediaCard memory card */
+ LDD_SDHC_CE_ATA /*!< Consumer Electronics ATA card */
+} LDD_SDHC_TCardType;
+
+/*! Card access properties */
+typedef struct {
+ uint16_t MaxBlockLength; /*!< Max. transferable block length */
+ bool MisalignBlock; /*!< Indicates if the data block can be spread over more than one physical block of the memory device */
+ bool PartialBlock; /*!< Indicates whether partial block sizes can be used in block access */
+} LDD_SDHC_TCardAccess;
+
+/*! Card erasion properties */
+typedef struct {
+ uint16_t SectorSize; /*!< The size of an erasable unit */
+ uint8_t Pattern; /*!< Memory content after erase */
+} LDD_SDHC_TCardErase;
+
+/*! Card write protection properties */
+typedef struct {
+ uint16_t GroupSize; /*!< The size of write protected group in number of erase groups */
+ bool Permanent; /*!< Indicates whether card is permanently write protected (read-only) */
+} LDD_SDHC_TCardWriteProtect;
+
+/*! Card capabilities */
+typedef struct {
+ uint8_t DataWidths; /*!< Bit mask of supported data bus widths */
+ uint8_t Operations; /*!< Bit mask of supported operations */
+ bool HighSpeed; /*!< Indicates whether the card supports high clock configuration (SD bus clock frequency higher than about 25MHz) */
+ bool HighCapacity; /*!< Indicates whether the card requires block addressing instead of byte addressing */
+ bool LowVoltage; /*!< Indicates whether the card supports the host's low voltage range */
+ LDD_SDHC_TCardAccess Read; /*!< Card data read access capabilities */
+ LDD_SDHC_TCardAccess Write; /*!< Card data write access capabilities */
+ LDD_SDHC_TCardErase Erase; /*!< Card data erasion capabilities */
+ LDD_SDHC_TCardWriteProtect WriteProtect; /*!< Write protection properties */
+} LDD_SDHC_TCardCaps;
+
+/*! Card features description */
+typedef struct {
+ LDD_SDHC_TCardType Type; /*!< Card type */
+ uint16_t BlockLength; /*!< Physical memory block length */
+ uint32_t BlockCount; /*!< Number of physical memory blocks */
+ LDD_SDHC_TCardCaps Caps; /*!< Card capabilities */
+} LDD_SDHC_TCardInfo;
+
+/*! Transfer operations */
+typedef enum {
+ LDD_SDHC_READ, /*!< Read operation */
+ LDD_SDHC_WRITE /*!< Write operation */
+} LDD_SDHC_TTransferOperation;
+
+/*! Transfer buffer descriptor */
+typedef struct {
+ uint16_t Size; /*!< Buffer data size */
+ uint8_t *DataPtr; /*!< Pointer to buffer data */
+} LDD_SDHC_TBufferDesc;
+
+/*! Voltage options */
+typedef enum {
+ LDD_SDHC_LOW_VOLTAGE, /*!< Low voltage */
+ LDD_SDHC_HIGH_VOLTAGE /*!< High voltage */
+} LDD_SDHC_TVoltage;
+
+/*! Write protection types */
+typedef enum {
+ LDD_SDHC_GROUP, /*!< Write protection by groups */
+ LDD_SDHC_CARD /*!< Whole card write protection */
+} LDD_SDHC_TWriteProtectType;
+
+/*! Component states */
+typedef enum {
+ LDD_SDHC_DISABLED, /*!< Disabled */
+ LDD_SDHC_RESET, /*!< Resetting card */
+ LDD_SDHC_IDLE, /*!< Idling */
+ LDD_SDHC_VOLTAGE_VALIDATION, /*!< Validating voltage */
+ LDD_SDHC_CARD_REGISTRATION, /*!< Registrating card */
+ LDD_SDHC_CARD_SELECTION, /*!< Selecting card */
+ LDD_SDHC_CARD_INFO_RETRIEVAL, /*!< Retrieving card info */
+ LDD_SDHC_TRANSFER, /*!< Transferring data */
+ LDD_SDHC_ERASION, /*!< Erasing blocks */
+ LDD_SDHC_IO_REG_TRANSFER, /*!< Transferring IO registers */
+ LDD_SDHC_DATA_WIDTH_SELECTION, /*!< Selecting data width */
+ LDD_SDHC_BUS_CLOCK_SELECTION, /*!< Selecting bus clock */
+ LDD_SDHC_WRITE_PROTECTION_SETUP, /*!< Setting up write protection */
+ LDD_SDHC_WRITE_PROTECTION_RETRIEVAL /*!< Retrieving write protection configuration */
+} LDD_SDHC_TStatus;
+
+/*! Operation completion error codes */
+typedef enum {
+ LDD_SDHC_ERR_OK, /*!< No error */
+ LDD_SDHC_ERR_DMA, /*!< DMA or block size error */
+ LDD_SDHC_ERR_NOT_SUPPORTED, /*!< Initiated operation is not supported by the card (supported operations are contained in the card information structure) */
+ LDD_SDHC_ERR_TIMEOUT, /*!< Command or data timeout */
+ LDD_SDHC_ERR_COMMAND_CRC, /*!< Command CRC check failed */
+ LDD_SDHC_ERR_DATA_CRC, /*!< Data CRC check failed */
+ LDD_SDHC_ERR_ADDRESS_OUT_OF_RANGE, /*!< The card address is beyond the card capacity */
+ LDD_SDHC_ERR_ADDRESS_MISALIGN, /*!< The card address does not align with physical blocks of the card */
+ LDD_SDHC_ERR_BLOCK_LEN_ERROR, /*!< Block length exceeds the maximum value for the card */
+ LDD_SDHC_ERR_WP_VIOLATION, /*!< Attempt to program a write protected block */
+ LDD_SDHC_ERR_CARD_IS_LOCKED, /*!< The card is locked by the host */
+ LDD_SDHC_ERR_WP_ERASE_SKIP, /*!< Only partial address space was erased due to existing write protected blocks */
+ LDD_SDHC_ERR_INTERNAL_FAILURE, /*!< Internal component error */
+ LDD_SDHC_ERR_CARD_FAILURE /*!< The card was unable to complete the operation */
+} LDD_SDHC_TError;
+
+/*
+** ===================================================================
+** DMA device types and constants
+** ===================================================================
+*/
+
+#define LDD_DMA_ON_COMPLETE 0x01U /*!< OnTransferComplete event mask. */
+#define LDD_DMA_ON_ERROR 0x02U /*!< OnError event mask. */
+
+#define LDD_DMA_UNKNOWN_ERROR 0x80000000U /*!< Unknown error. */
+#define LDD_DMA_CHANNEL_PRIORITY_ERROR 0x4000U /*!< Channel priority error. */
+#define LDD_DMA_SOURCE_ADDRESS_ERROR 0x80U /*!< Address inconsistency with transfer size error. */
+#define LDD_DMA_SOURCE_OFFSET_ERROR 0x40U /*!< Offset inconsistency with transfer size error. */
+#define LDD_DMA_DESTINATION_ADDRESS_ERROR 0x20U /*!< Address inconsistency with transfer size error. */
+#define LDD_DMA_DESTINATION_OFFSET_ERROR 0x10U /*!< Offset inconsistency with transfer size error. */
+#define LDD_DMA_COUNT_ERROR 0x08U /*!< Byte count inconsistency with transfer sizes or transfer count error. */
+#define LDD_DMA_SCATTER_GATHER_ERROR 0x04U /*!< Scatter/gather configuration error. */
+#define LDD_DMA_SOURCE_BUS_ERROR 0x02U /*!< Bus error on a source read. */
+#define LDD_DMA_DESTINATION_BUS_ERROR 0x01U /*!< Bus error on a destination write. */
+
+#define LDD_DMA_CHANNEL_0_MASK 0x01UL /*!< DMA channel 0 mask. */
+#define LDD_DMA_CHANNEL_1_MASK 0x02UL /*!< DMA channel 1 mask. */
+#define LDD_DMA_CHANNEL_2_MASK 0x04UL /*!< DMA channel 2 mask. */
+#define LDD_DMA_CHANNEL_3_MASK 0x08UL /*!< DMA channel 3 mask. */
+#define LDD_DMA_CHANNEL_4_MASK 0x10UL /*!< DMA channel 4 mask. */
+#define LDD_DMA_CHANNEL_5_MASK 0x20UL /*!< DMA channel 5 mask. */
+#define LDD_DMA_CHANNEL_6_MASK 0x40UL /*!< DMA channel 6 mask. */
+#define LDD_DMA_CHANNEL_7_MASK 0x80UL /*!< DMA channel 7 mask. */
+#define LDD_DMA_CHANNEL_8_MASK 0x0100UL /*!< DMA channel 8 mask. */
+#define LDD_DMA_CHANNEL_9_MASK 0x0200UL /*!< DMA channel 9 mask. */
+#define LDD_DMA_CHANNEL_10_MASK 0x0400UL /*!< DMA channel 10 mask. */
+#define LDD_DMA_CHANNEL_11_MASK 0x0800UL /*!< DMA channel 11 mask. */
+#define LDD_DMA_CHANNEL_12_MASK 0x1000UL /*!< DMA channel 12 mask. */
+#define LDD_DMA_CHANNEL_13_MASK 0x2000UL /*!< DMA channel 13 mask. */
+#define LDD_DMA_CHANNEL_14_MASK 0x4000UL /*!< DMA channel 14 mask. */
+#define LDD_DMA_CHANNEL_15_MASK 0x8000UL /*!< DMA channel 15 mask. */
+#define LDD_DMA_CHANNEL_16_MASK 0x00010000UL /*!< DMA channel 16 mask. */
+#define LDD_DMA_CHANNEL_17_MASK 0x00020000UL /*!< DMA channel 17 mask. */
+#define LDD_DMA_CHANNEL_18_MASK 0x00040000UL /*!< DMA channel 18 mask. */
+#define LDD_DMA_CHANNEL_19_MASK 0x00080000UL /*!< DMA channel 19 mask. */
+#define LDD_DMA_CHANNEL_20_MASK 0x00100000UL /*!< DMA channel 21 mask. */
+#define LDD_DMA_CHANNEL_21_MASK 0x00200000UL /*!< DMA channel 22 mask. */
+#define LDD_DMA_CHANNEL_22_MASK 0x00400000UL /*!< DMA channel 23 mask. */
+#define LDD_DMA_CHANNEL_23_MASK 0x00800000UL /*!< DMA channel 24 mask. */
+#define LDD_DMA_CHANNEL_24_MASK 0x01000000UL /*!< DMA channel 25 mask. */
+#define LDD_DMA_CHANNEL_25_MASK 0x02000000UL /*!< DMA channel 26 mask. */
+#define LDD_DMA_CHANNEL_26_MASK 0x04000000UL /*!< DMA channel 27 mask. */
+#define LDD_DMA_CHANNEL_27_MASK 0x08000000UL /*!< DMA channel 28 mask. */
+#define LDD_DMA_CHANNEL_28_MASK 0x10000000UL /*!< DMA channel 29 mask. */
+#define LDD_DMA_CHANNEL_29_MASK 0x20000000UL /*!< DMA channel 30 mask. */
+#define LDD_DMA_CHANNEL_30_MASK 0x40000000UL /*!< DMA channel 31 mask. */
+#define LDD_DMA_CHANNEL_31_MASK 0x80000000UL /*!< DMA channel 32 mask. */
+
+/* Action executed after request and transfer service completes */
+#define LDD_DMA_NO_ACTION 0x00U /*!< No action performed after request serviced. */
+#define LDD_DMA_DESTINATION_ADDRESS_ADJUSTMENT 0x01U /*!< Destination address adjustment after request serviced. */
+#define LDD_DMA_SOURCE_ADDRESS_ADJUSTMENT 0x02U /*!< Source address adjustment after request serviced. */
+#define LDD_DMA_ADDRESS_ADJUSTMENT 0x01U /*!< Address adjustment after transfer completed. */
+#define LDD_DMA_SCATTER_GATHER 0x02U /*!< Scatter/gather performed after transfer completed. */
+
+typedef void LDD_DMA_TData;
+typedef uint8_t LDD_DMA_TTransactionSize; /* Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */
+typedef uint32_t LDD_DMA_TTransactionCount;
+typedef uint32_t LDD_DMA_TRequestCount;
+typedef uint32_t LDD_DMA_TTransferDataSize;
+
+typedef uint32_t LDD_DMA_TAddress; /*!< Type specifying the address parameter used by the DMA component's methods. */
+typedef int32_t LDD_DMA_TAddressOffset; /*!< Type specifying the address signed offset parameter used by the DMA component's methods. */
+typedef uint32_t LDD_DMA_TByteCount; /*!< Type specifying the byte count/minor loop count parameter used by the DMA component's methods. */
+typedef uint8_t LDD_DMA_TTransferSize; /*!< Type specifying the transfer size parameter used by the DMA component's methods. See the DMA_PDD header file for detail description of allowed values. */
+typedef uint8_t LDD_DMA_TModuloSize; /*!< Type specifying the modulo size parameter used by the DMA component's methods. */
+ /*!< This value power of two represents size of used circular buffer (0U - buffer disabled). See the MCU manual for detail description of allowed values. */
+typedef uint8_t LDD_DMA_TTriggerSource; /*!< Type specifying the trigger source signal number. See the MCU manual for detail description of allowed values. */
+typedef uint8_t LDD_DMA_TChannelNumber; /*!< Type specifying the DMA channel number. See the MCU manual for detail description of allowed values. */
+typedef uint8_t LDD_DMA_TRecordNumber; /*!< Type specifying the DMA descriptor record number. */
+typedef uint32_t LDD_DMA_TChannelMask; /*!< Type specifying the DMA channel mask. For possible values see channel mask constants. */
+typedef uint8_t LDD_DMA_TChannelPriority; /*!< Type specifying the DMA channel priority number. See the MCU manual for detail description of allowed values. */
+typedef uint16_t LDD_DMA_TOuterLoopCount; /*!< Type specifying the transfer outer/major loop count. */
+typedef uint8_t LDD_DMA_TAfterRequest; /*!< Type specifying the operation executed after request service is completed. */
+typedef uint8_t LDD_DMA_TAfterTransfer; /*!< Type specifying the operation executed after transfer service is completed. */
+typedef uint8_t LDD_DMA_TBandwidthControl; /*!< Type specifying the bandwidth control. See the DMA_PDD header file for detail description of allowed values. */
+typedef uint32_t LDD_DMA_TErrorFlags; /*!< DMA controller error flags. See the DMA_LDD component's header file for detail description of allowed values. */
+
+/*! Type specifying a DMA channel status. */
+typedef enum {
+ LDD_DMA_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */
+ LDD_DMA_BUSY, /*!< Channel is active, request is serviced. */
+ LDD_DMA_DONE, /*!< Transfer is completed, waiting to start of next transfer. */
+ LDD_DMA_ERROR /*!< Error detected. */
+} LDD_DMA_TChannelStatus;
+
+/*! Type specifying a DMA transfer state. */
+typedef enum {
+ LDD_DMA_TRANSFER_IDLE, /*!< Channel is idle, no request is serviced nor transfer completed. */
+ LDD_DMA_TRANSFER_BUSY, /*!< Channel is active, request is serviced. */
+ LDD_DMA_TRANSFER_ERROR /*!< Error detected. */
+} LDD_DMA_TTransferState;
+
+/*! Type specifying the DMA transfer mode. */
+typedef enum {
+ LDD_DMA_CYCLE_STEAL_TRANSFERS, /*!< Only single read/write transfer is done per one service request. */
+ LDD_DMA_SINGLE_TRANSFER, /*!< Transfer of all bytes defined by Data size is done after single service request. */
+ LDD_DMA_NESTED_TRANSFERS /*!< Sequence of transfers triggered by service requests. One request transfers number of bytes defined by Byte count value. */
+} LDD_DMA_TTransferMode;
+
+/*! Type specifying the DMA trigger source type. */
+typedef enum {
+ LDD_DMA_SW_TRIGGER, /*!< Explicit software trigger. */
+ LDD_DMA_HW_TRIGGER, /*!< Peripheral device trigger. */
+ LDD_DMA_ALWAYS_ENABLED_TRIGGER /*!< Always enabled trigger. */
+} LDD_DMA_TTriggerType;
+
+/*! Type specifying the DMA error information structure. */
+typedef struct {
+ LDD_DMA_TChannelNumber ChannelNumber; /*!< Last error recorded channel number. */
+ LDD_DMA_TErrorFlags ErrorFlags; /*!< Channel error flags. */
+} LDD_DMA_TError;
+
+/*! Type specifying the DMA Transfer descriptor information structure. */
+typedef struct {
+ LDD_TUserData *UserDataPtr; /*!< User device data structure pointer to be returned by the DMA_LDD component's ISR to the dynamic callback of this transfer descriptor. */
+ LDD_DMA_TAddress SourceAddress; /*!< Address of a DMA transfer source data. */
+ LDD_DMA_TAddressOffset SourceAddressOffset; /*!< Offset to be added to the source address after each elemental read operation. */
+ LDD_DMA_TTransferSize SourceTransferSize; /*!< Source data transfer size (size of a elemental read operation). See the DMA_PDD header file for detail description of allowed values. */
+ LDD_DMA_TModuloSize SourceModuloSize; /*!< Source address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */
+ LDD_DMA_TAddress DestinationAddress; /*!< Address of a DMA transfer destination. */
+ LDD_DMA_TAddressOffset DestinationAddressOffset; /*!< Offset to be added to the destination address after each elemental write operation. */
+ LDD_DMA_TTransferSize DestinationTransferSize; /*!< Destination data transfer size (size of a elemental write operation). See the DMA_PDD header file for detail description of allowed values. */
+ LDD_DMA_TModuloSize DestinationModuloSize; /*!< Destination address modulo size. For the description of allowed values see the LDD_DMA_TModuloSize type declaration. */
+ LDD_DMA_TTransferMode TransferMode; /*!< Selects DMA transfer mode. For the description of allowed values see the LDD_DMA_TTransferMode type declaration. */
+ LDD_DMA_TByteCount ByteCount; /*!< Size of data in bytes to be transferred in single transfer. */
+ LDD_DMA_TOuterLoopCount OuterLoopCount; /*!< Number of the outer loop iteration in the Nested operation mode, otherwise should have value of one. */
+ bool InnerLoopChannelLink; /*!< TRUE - Inner loop channel linking enabled (if the nested operation is used, then this item enables the minor (inner) loop channel linking). */
+ LDD_DMA_TChannelNumber InnerLoopLinkedChannel; /*!< Linked DMA channel number (used only if the InnerLoopChannelLink item is set TRUE) */
+ bool OuterLoopChannelLink; /*!< TRUE - Outer (major) loop channel linking is enabled. Enables channel linking after transfer completes. */
+ LDD_DMA_TChannelNumber OuterLoopLinkedChannel; /*!< Outer (major) loop linked DMA channel number (used only if the OuterLoopChannelLink item is set TRUE). */
+ LDD_DMA_TAfterRequest AfterRequestComplete; /*!< Type of an action after the elemental read/write operation is done. For the description of allowed values see the LDD_DMA_TAfterRequest type declaration. */
+ LDD_DMA_TAddressOffset AddressOffset; /*!< Address offset value. Address specified in AfterRequestComplete item is adjusted by stored value. See the LDD_DMA_TAfterRequest type declaration. */
+ LDD_DMA_TAfterTransfer AfterTransferComplete; /*!< Type of an action executed after the last transfer operation is done. For the description of allowed values see the LDD_DMA_TAfterTransfer type declaration. */
+ LDD_DMA_TAddressOffset SourceAddressAdjustment; /*!< Source address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */
+ LDD_DMA_TAddressOffset DestinationAddressAdjustment; /*!< Destination address adjustment value. Used only if the AfterTransferComplete item is set to LDD_DMA_ADDRESS_ADJUSTMENT. */
+ LDD_DMA_TAddress ScatterGatherAddress; /*!< Scatter / gather address. Used only if the AfterTransferComplete item is set to LDD_DMA_SCATTER_GATHER. */
+ LDD_DMA_TBandwidthControl BandwidthControl; /*!< DMA channel bandwidth control. See the DMA_PDD header file for detail description of allowed values. */
+ bool ChannelAutoSelection; /*!< TRUE - DMA channel autoselection engine is used. FALSE - DMA fixed channel is used. */
+ LDD_DMA_TChannelNumber ChannelNumber; /*!< If ChannelAutoSelection is FALSE this item contains fixed channel number. If ChannelAutoSelection is TRUE then after allocation this item is filled by autoselected channel number. */
+ LDD_DMA_TTriggerType TriggerType; /*!< DMA transfer trigger type. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */
+ LDD_DMA_TTriggerSource TriggerSource; /*!< Trigger source number. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */
+ bool PeriodicTrigger; /*!< TRUE - periodic trigger is required, FALSE - periodic trigger is not required. */
+ bool DisableAfterRequest; /*!< TRUE - DMA transfer request is automatically disabled after transfer complete. */
+ bool Interrupts; /*!< TRUE - interrupts are requested. */
+ bool OnComplete; /*!< TRUE - event is enabled during initialization. */
+ bool OnHalfComplete; /*!< TRUE - event is enabled during initialization. */
+ bool OnError; /*!< TRUE - event is enabled during initialization. */
+ void (*OnCompleteEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnComplete event, NULL if event is not used. */
+ void (*OnErrorEventPtr)(LDD_TUserData* UserDataPtr); /*!< Pointer to the OnError event, NULL if event is not used. */
+ bool ChannelEnabled; /*!< TRUE - DMA channel is allocated and used by DMATransfer component. */
+ bool DmaMux0; /*!< TRUE - DMA channel can be connected to DMA MUX0 */
+ bool DmaMux1; /*!< TRUE - DMA channel can be connected to DMA MUX1 */
+ LDD_DMA_TTriggerSource TriggerSourceMux1; /*!< Trigger source number used when channel connected to DMAMUX1. For the description of allowed values see the LDD_DMA_TBTriggerType declaration. */
+} LDD_DMA_TTransferDescriptor;
+
+typedef LDD_DMA_TTransferDescriptor *LDD_DMA_TTransferDescriptorPtr; /*!< Type specifying address of the DMA Transfer descriptor structure. */
+
+/*
+** ===================================================================
+** SPI device types and constants - SPIMaster_LDD
+** ===================================================================
+*/
+
+#define LDD_SPIMASTER_INPUT_PIN 0x01U /*!< Input pin mask */
+#define LDD_SPIMASTER_OUTPUT_PIN 0x02U /*!< Output pin mask */
+#define LDD_SPIMASTER_CLK_PIN 0x04U /*!< Clock pin mask */
+#define LDD_SPIMASTER_CS_0_PIN 0x08U /*!< Chip select 0 pin mask */
+#define LDD_SPIMASTER_CS_1_PIN 0x10U /*!< Chip select 1 pin mask */
+#define LDD_SPIMASTER_CS_2_PIN 0x20U /*!< Chip select 2 pin mask */
+#define LDD_SPIMASTER_CS_3_PIN 0x40U /*!< Chip select 3 pin mask */
+#define LDD_SPIMASTER_CS_4_PIN 0x80U /*!< Chip select 4 pin mask */
+#define LDD_SPIMASTER_CS_5_PIN 0x0100U /*!< Chip select 5 pin mask */
+#define LDD_SPIMASTER_CS_6_PIN 0x0200U /*!< Chip select 6 pin mask */
+#define LDD_SPIMASTER_CS_7_PIN 0x0400U /*!< Chip select 7 pin mask */
+#define LDD_SPIMASTER_CSS_PIN 0x0800U /*!< Chip select strobe pin mask */
+
+#define LDD_SPIMASTER_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */
+#define LDD_SPIMASTER_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */
+#define LDD_SPIMASTER_ON_ERROR 0x04U /*!< OnError event mask */
+
+#define LDD_SPIMASTER_RX_OVERFLOW 0x01U /*!< Receiver overflow */
+#define LDD_SPIMASTER_PARITY_ERROR 0x02U /*!< Parity error */
+#define LDD_SPIMASTER_RX_DMA_ERROR 0x04U /*!< Receive DMA channel error */
+#define LDD_SPIMASTER_TX_DMA_ERROR 0x08U /*!< Transmit DMA channel error */
+
+typedef uint32_t LDD_SPIMASTER_TError; /*!< Communication error type */
+
+/*! Communication statistics */
+typedef struct {
+ uint32_t RxChars; /*!< Number of received characters */
+ uint32_t TxChars; /*!< Number of transmitted characters */
+ uint32_t RxParityErrors; /*!< Number of receiver parity errors, which have occured */
+ uint32_t RxOverruns; /*!< Number of receiver overruns, which have occured */
+} LDD_SPIMASTER_TStats;
+
+/*
+** ===================================================================
+** SPI device types and constants - SPISlave_LDD
+** ===================================================================
+*/
+
+#define LDD_SPISLAVE_INPUT_PIN 0x01U /*!< Input pin mask */
+#define LDD_SPISLAVE_OUTPUT_PIN 0x02U /*!< Output pin mask */
+#define LDD_SPISLAVE_CLK_PIN 0x04U /*!< Clock pin mask */
+#define LDD_SPISLAVE_SS_PIN 0x08U /*!< Slave select pin mask */
+
+#define LDD_SPISLAVE_ON_BLOCK_RECEIVED 0x01U /*!< OnBlockReceived event mask */
+#define LDD_SPISLAVE_ON_BLOCK_SENT 0x02U /*!< OnBlockSent event mask */
+#define LDD_SPISLAVE_ON_ERROR 0x04U /*!< OnError event mask */
+
+#define LDD_SPISLAVE_RX_OVERFLOW 0x01U /*!< Receiver overflow */
+#define LDD_SPISLAVE_TX_UNDERFLOW 0x02U /*!< Transmitter underflow */
+#define LDD_SPISLAVE_PARITY_ERROR 0x04U /*!< Parity error */
+#define LDD_SPISLAVE_RX_DMA_ERROR 0x08U /*!< Receive DMA channel error */
+#define LDD_SPISLAVE_TX_DMA_ERROR 0x10U /*!< Transmit DMA channel error */
+
+typedef uint32_t LDD_SPISLAVE_TError; /*!< Communication error type */
+
+/*! Communication statistics */
+typedef struct {
+ uint32_t RxChars; /*!< Number of received characters */
+ uint32_t TxChars; /*!< Number of transmitted characters */
+ uint32_t RxParityErrors; /*!< Number of receiver parity errors, which have occured */
+ uint32_t RxOverruns; /*!< Number of receiver overruns, which have occured */
+ uint32_t TxUnderruns; /*!< Number of transmitter underruns, which have occured */
+} LDD_SPISLAVE_TStats;
+
+/*
+** ===================================================================
+** I2S device types and constants
+** ===================================================================
+*/
+
+#define LDD_SSI_INPUT_PIN 0x01U /*!< Input pin mask */
+#define LDD_SSI_OUTPUT_PIN 0x02U /*!< Output pin mask */
+#define LDD_SSI_RX_CLK_PIN 0x04U /*!< Rx clock pin mask */
+#define LDD_SSI_TX_CLK_PIN 0x08U /*!< Tx clock pin mask */
+#define LDD_SSI_RX_FS_PIN 0x10U /*!< Rx frame sync pin mask */
+#define LDD_SSI_TX_FS_PIN 0x20U /*!< Tx frame sync pin mask */
+#define LDD_SSI_MCLK_PIN 0x40U /*!< Master clock pin mask */
+#define LDD_SSI_INPUT_PIN_CHANNEL_0 0x80U /*!< Input pin mask for data channel 0 */
+#define LDD_SSI_INPUT_PIN_CHANNEL_1 0x0100U /*!< Input pin mask for data channel 1 */
+#define LDD_SSI_OUTPUT_PIN_CHANNEL_0 0x0200U /*!< Output pin mask for data channel 0 */
+#define LDD_SSI_OUTPUT_PIN_CHANNEL_1 0x0400U /*!< Output pin mask for data channel 1 */
+
+#define LDD_SSI_ON_BLOCK_RECEIVED 0x01u /*!< OnBlockReceived event mask */
+#define LDD_SSI_ON_BLOCK_SENT 0x02u /*!< OnBlockSent event mask */
+#define LDD_SSI_ON_ERROR 0x04u /*!< OnError event mask */
+#define LDD_SSI_ON_BLOCK_RECEIVED_1 0x08u /*!< OnBlockReceived event mask for second channel */
+#define LDD_SSI_ON_BLOCK_SENT_1 0x10u /*!< OnBlockSent event mask for second channel */
+#define LDD_SSI_ON_RECEIVE_FRAME_SYNC 0x20u /*!< OnReceiveFrameSync event mask for second channel */
+#define LDD_SSI_ON_TRANSMIT_FRAME_SYNC 0x40u /*!< OnTransmitFrameSync event mask for second channel */
+#define LDD_SSI_ON_RECEIVE_LAST_SLOT 0x80u /*!< OnReceiveLastSlot event mask for second channel */
+#define LDD_SSI_ON_TRANSMIT_LAST_SLOT 0x0100u /*!< OnTransmitLastSlot event mask for second channel */
+#define LDD_SSI_ON_RECEIVE_COMPLETE 0x0200u /*!< OnReceiveComplete event mask for second channel */
+#define LDD_SSI_ON_TRANSMIT_COMPLETE 0x0400u /*!< OnTransmitComplete event mask for second channel */
+#define LDD_SSI_ON_A_C_9_7_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */
+#define LDD_SSI_ON_AC_97_TAG_UPDATED 0x0800u /*!< OnAC97TagUpdated event mask for second channel */
+#define LDD_SSI_ON_A_C_9_7_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */
+#define LDD_SSI_ON_AC_97_COMMAND_ADDRESS_UPDATED 0x1000u /*!< OnAC97CommandAddressUpdated event mask for second channel */
+#define LDD_SSI_ON_A_C_9_7_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */
+#define LDD_SSI_ON_AC_97_COMMAND_DATA_UPDATED 0x2000u /*!< OnAC97CommandDataUpdated event mask for second channel */
+
+#define LDD_SSI_RECEIVER 0x01U /*!< Receive section of the device. */
+#define LDD_SSI_TRANSMITTER 0x02U /*!< Transmit section of the device. */
+
+#define LDD_SSI_RX_OVERFLOW 0x01U /*!< Receiver overflow */
+#define LDD_SSI_RX_OVERFLOW_1 0x02U /*!< Receiver overflow 1 */
+#define LDD_SSI_RX_SYNC_ERROR 0x04U /*!< Receiver frame sync error */
+#define LDD_SSI_RX_DMA_ERROR 0x08U /*!< Receiver DMA error */
+
+#define LDD_SSI_TX_UNDERFLOW 0x10U /*!< Transmitter underflow */
+#define LDD_SSI_TX_UNDERFLOW_1 0x20U /*!< Transmitter underflow 1 */
+#define LDD_SSI_TX_SYNC_ERROR 0x40U /*!< Transmitter frame sync error */
+#define LDD_SSI_TX_DMA_ERROR 0x80U /*!< Transmitter DMA error */
+
+#define LDD_SSI_RX_FRAME_COMPLETE 0x01U /*!< Receive frame is finished after disabling transfer */
+#define LDD_SSI_TX_FRAME_COMPLETE 0x02U /*!< Transmit frame is finished after disabling transfer */
+#define LDD_SSI_RX_FRAME_SYNC 0x04U /*!< Receiver frame sync */
+#define LDD_SSI_TX_FRAME_SYNC 0x08U /*!< Transmit frame sync */
+#define LDD_SSI_RX_LAST_SLOT 0x10U /*!< Receive last time slot */
+#define LDD_SSI_TX_LAST_SLOT 0x20U /*!< Transmit last time slot */
+#define LDD_SSI_AC97_TAG 0x40U /*!< AC97 tag updated */
+#define LDD_SSI_AC97_COMMAND_ADDRESS 0x80U /*!< AC97 command address updated */
+#define LDD_SSI_AC97_COMMAND_DATA 0x0100U /*!< AC97 command data updated */
+
+typedef uint8_t LDD_SSI_TSectionMask; /*!< Device section type */
+
+typedef uint32_t LDD_SSI_TError; /*!< Communication error type */
+
+typedef uint32_t LDD_SSI_TComStatus; /*!< Communication status type */
+
+/*! Group of pointers to data blocks. */
+typedef struct {
+ LDD_TData *Channel0Ptr; /*!< Pointer to data block to send/received via data channel 0 */
+ LDD_TData *Channel1Ptr; /*!< Pointer to data block to send/received via data channel 1 */
+} LDD_SSI_TDataBlocks;
+
+/*! Command type */
+typedef enum {
+ LDD_SSI_READ_COMMAND = 0x08u,
+ LDD_SSI_WRITE_COMMAND = 0x10u
+} LDD_SSI_TAC97CommandType;
+
+/*! AC97 command */
+typedef struct {
+ LDD_SSI_TAC97CommandType Type; /*!< Command type */
+ uint32_t Address; /*!< Command address */
+ uint32_t Data; /*!< Command data */
+} LDD_SSI_TAC97Command;
+
+/*! Communication statistics */
+typedef struct {
+ uint32_t RxChars; /*!< Number of received characters */
+ uint32_t TxChars; /*!< Number of transmitted characters */
+ uint32_t RxOverruns; /*!< Number of receiver overruns, which have occured */
+ uint32_t TxUnderruns; /*!< Number of transmitter underruns, which have occured */
+ uint32_t RxChars1; /*!< Number of received characters for second channel */
+ uint32_t TxChars1; /*!< Number of transmitted characters for second channel */
+ uint32_t RxOverruns1; /*!< Number of receiver overruns, which have occured for second channel */
+ uint32_t TxUnderruns1; /*!< Number of transmitter underruns, which have occured for second channel */
+} LDD_SSI_TStats;
+
+/*
+** ===================================================================
+** RTC device types and constants
+** ===================================================================
+*/
+
+#define LDD_RTC_ON_SECOND 0x10u /*!< OnSecond event mask */
+#define LDD_RTC_ON_MONOTONIC_OVERFLOW 0x08u /*!< OnMonotonicCounter event mask */
+#define LDD_RTC_ON_ALARM 0x04u /*!< OnAlarm event mask */
+#define LDD_RTC_ON_TIME_OVERFLOW 0x02u /*!< OnTimeOverflow event mask */
+#define LDD_RTC_ON_TIME_INVALID 0x01u /*!< OnTimeInvalid event mask */
+#define LDD_RTC_ON_STOPWATCH 0x0100u /*!< OnStopwatch event mask */
+
+/*! Structure used for time operation */
+typedef struct {
+ uint32_t Second; /*!< seconds (0 - 59) */
+ uint32_t Minute; /*!< minutes (0 - 59) */
+ uint32_t Hour; /*!< hours (0 - 23) */
+ uint32_t DayOfWeek; /*!< day of week (0-Sunday, .. 6-Saturday) */
+ uint32_t Day; /*!< day (1 - 31) */
+ uint32_t Month; /*!< month (1 - 12) */
+ uint32_t Year; /*!< year */
+} LDD_RTC_TTime;
+
+
+
+/*
+** ===================================================================
+** CRC device types and constants
+** ===================================================================
+*/
+
+#define LDD_CRC_16_SEED_LOW 0x00U /*!< CRC 16bit seed low */
+#define LDD_CRC_16_POLY_LOW 0x8005U /*!< CRC 16bit poly low */
+#define LDD_CRC_32_SEED_LOW 0xFFFFU /*!< CRC 32bit seed low */
+#define LDD_CRC_32_SEED_HIGH 0xFFFFU /*!< CRC 32bit seed high */
+#define LDD_CRC_32_POLY_LOW 0x1DB7U /*!< CRC 32bit poly low */
+#define LDD_CRC_32_POLY_HIGH 0x04C1U /*!< CRC 32bit poly high */
+#define LDD_CRC_CCITT_SEED_LOW 0xFFFFU /*!< CRC CCITT seed low */
+#define LDD_CRC_CCITT_POLY_LOW 0x1021U /*!< CRC CCITT poly low */
+#define LDD_CRC_MODBUS_16_SEED_LOW 0xFFFFU /*!< CRC MODBUS16 seed low */
+#define LDD_CRC_MODBUS_16_POLY_LOW 0x8005U /*!< CRC MODBUS16 poly low */
+#define LDD_CRC_KERMIT_SEED_LOW 0x00U /*!< CRC KERMIT seed low */
+#define LDD_CRC_KERMIT_POLY_LOW 0x1021U /*!< CRC KERMIT poly low */
+#define LDD_CRC_DNP_SEED_LOW 0x00U /*!< CRC DNP seed low */
+#define LDD_CRC_DNP_POLY_LOW 0x3D65U /*!< CRC DNP poly low */
+
+/*! Transpose type */
+typedef enum {
+ LDD_CRC_NO_TRANSPOSE = 0, /*!< No transposition */
+ LDD_CRC_BITS = 1, /*!< Bits are transposed */
+ LDD_CRC_BITS_AND_BYTES = 2, /*!< Bits and bytes are transposed */
+ LDD_CRC_BYTES = 3 /*!< Bytes are transposed */
+} LDD_CRC_TTransposeType;
+
+/*! CRC standard */
+typedef enum {
+ LDD_CRC_16, /*!< CRC16 standard */
+ LDD_CRC_CCITT, /*!< CCITT standard */
+ LDD_CRC_MODBUS_16, /*!< MODBUS16 standard */
+ LDD_CRC_KERMIT, /*!< KERMIT standard */
+ LDD_CRC_DNP, /*!< DNP standard */
+ LDD_CRC_32, /*!< CRC32 standard */
+ LDD_CRC_USER /*!< User defined type */
+} LDD_CRC_TCRCStandard;
+
+/*! User CRC standard */
+typedef struct {
+ bool Width32bit; /*!< 32bit CRC? */
+ bool ResultXORed; /*!< Result XORed? */
+ uint16_t SeedLow; /*!< Seed low value */
+ uint16_t SeedHigh; /*!< Seed high value */
+ uint16_t PolyLow; /*!< Poly low value */
+ uint16_t PolyHigh; /*!< Poly high value */
+ LDD_CRC_TTransposeType InputTransposeMode; /*!< Input transpose type */
+ LDD_CRC_TTransposeType OutputTransposeMode; /*!< Output transpose type */
+} LDD_CRC_TUserCRCStandard;
+
+/*
+** ===================================================================
+** RNG device types and constants
+** ===================================================================
+*/
+
+
+#define LDD_RNG_LFSR_ERROR 0x01U /*!< Linear feedback shift register error */
+#define LDD_RNG_OSCILLATOR_ERROR 0x02U /*!< Oscillator error */
+#define LDD_RNG_SELF_TEST_ERROR 0x04U /*!< Self test error */
+#define LDD_RNG_STATISTICAL_ERROR 0x08U /*!< LStatistical test error */
+#define LDD_RNG_FIFO_UNDERFLOW_ERROR 0x10U /*!< FIFO underflow error */
+
+#define LDD_RNG_SELF_TETS_RESEED_ERROR 0x00200000U /*!< Reseed self test fail */
+#define LDD_RNG_SELF_TEST_PRNG_ERROR 0x00400000U /*!< PRNG self test fail */
+#define LDD_RNG_SELF_TEST_TRNG_ERROR 0x00800000U /*!< TRNG self test fail */
+#define LDD_RNG_MONOBIT_TEST_ERROR 0x01000000U /*!< Monobit test fail */
+#define LDD_RNG_LENGTH_1_RUN_TEST_ERROR 0x02000000U /*!< Length 1 run test fail */
+#define LDD_RNG_LENGTH_2_RUN_TEST_ERROR 0x04000000U /*!< Length 2 run test fail */
+#define LDD_RNG_LENGTH_3_RUN_TEST_ERROR 0x08000000U /*!< Length 3 run test fail */
+#define LDD_RNG_LENGTH_4_RUN_TEST_ERROR 0x10000000U /*!< Length 4 run test fail */
+#define LDD_RNG_LENGTH_5_RUN_TEST_ERROR 0x20000000U /*!< Length 5 run test fail */
+#define LDD_RNG_LENGTH_6_RUN_TEST_ERROR 0x40000000U /*!< Length 6 run test fail */
+#define LDD_RNG_LONG_RUN_TEST_ERROR 0x80000000U /*!< Long run test fail */
+
+#define LDD_RNG_ON_SEED_GENERATION_DONE 0x01U /*!< OnSeedGenerationDone event mask */
+#define LDD_RNG_ON_SELF_TEST_DONE 0x02U /*!< OnSelfTestDone event mask */
+#define LDD_RNG_ON_ERROR_LFSR 0x04U /*!< OnErrorLFSR event mask */
+#define LDD_RNG_ON_OSC_ERROR 0x08U /*!< OnOscError event mask */
+#define LDD_RNG_ON_SELF_TEST_ERROR 0x10U /*!< OnSelfTestError event mask */
+#define LDD_RNG_ON_STATISTICAL_ERROR 0x20U /*!< OnStatisticalError event mask */
+#define LDD_RNG_ON_FIFO_UNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */
+#define LDD_RNG_ON_FIFOUNDER_FLOW_ERROR 0x40U /*!< OnFIFOUnderFlowError event mask */
+
+#define LDD_RNG_STATUS_ERROR 0xFFFFU /*!< Error in RNG module flag */
+#define LDD_RNG_STATUS_NEW_SEED_DONE 0x40U /*!< New seed done flag */
+#define LDD_RNG_STATUS_SEED_DONE 0x20U /*!< Seed done flag */
+#define LDD_RNG_STATUS_SELF_TEST_DONE 0x10U /*!< Self test done flag */
+#define LDD_RNG_STATUS_RESEED_NEEDED 0x08U /*!< Reseed needed flag */
+#define LDD_RNG_STATUS_SLEEP 0x04U /*!< RNG in sleep mode */
+#define LDD_RNG_STATUS_BUSY 0x02U /*!< RNG busy flag */
+
+
+/*
+** ===================================================================
+** RNGA device types and constants
+** ===================================================================
+*/
+
+#define LDD_RNG_ON_ERROR 0x01U /*!< OnError event mask */
+
+#define LDD_RNG_STATUS_SECURITY_VIOLATION 0x01U /*!< Security violation occured */
+#define LDD_RNG_STATUS_LAST_READ_UNDERFLOW 0x02U /*!< Last read from RNGA caused underflow error */
+#define LDD_RNG_STATUS_OUT_REG_UNDERFLOW 0x04U /*!< The RNGA Output Register has been read while empty since last read of the RNGA Status Register. */
+#define LDD_RNG_STATUS_ERR_INT_PENDING 0x08U /*!< Error interrupt pending */
+#define LDD_RNG_STATUS_SLEEP_MODE 0x10U /*!< Sleep mode enabled */
+
+/*! RNGA sleep mode */
+typedef enum {
+ LDD_RNG_SLEEP_ENABLED, /*!< RNGA is in sleep mode */
+ LDD_RNG_SLEEP_DISABLED /*!< RNGA is running */
+} LDD_RNG_TSleepMode;
+
+/*
+** ===================================================================
+** DryIce device types and constants
+** ===================================================================
+*/
+
+#define LDD_DRY_ON_TAMPER_DETECTED 0x01U /*!< OnTamperDetected event mask */
+
+/* Tamper flags */
+#define LDD_DRY_TIME_OVERFLOW 0x04U /*!< RTC time overflow has occurred. */
+#define LDD_DRY_MONOTONIC_OVERFLOW 0x08U /*!< RTC monotonic overflow has occurred. */
+#define LDD_DRY_VOLTAGE_TAMPER 0x10U /*!< VBAT voltage is outside of the valid range. */
+#define LDD_DRY_CLOCK_TAMPER 0x20U /*!< The 32.768 kHz clock source is outside the valid range. */
+#define LDD_DRY_TEMPERATURE_TAMPER 0x40U /*!< The junction temperature is outside of specification. */
+#define LDD_DRY_SECURITY_TAMPER 0x80U /*!< The (optional) security module asserted its tamper detect. */
+#define LDD_DRY_FLASH_SECURITY 0x0100U /*!< The flash security is disabled. */
+#define LDD_DRY_TEST_MODE 0x0200U /*!< Any test mode has been entered. */
+/* Tamper flags indicating that the pin does not equal its expected value and was not filtered by the glitch filter (if enabled). */
+#define LDD_DRY_TAMPER_PIN_0 0x00010000U /*!< Mismatch on tamper pin 0. */
+#define LDD_DRY_TAMPER_PIN_1 0x00020000U /*!< Mismatch on tamper pin 1. */
+#define LDD_DRY_TAMPER_PIN_2 0x00040000U /*!< Mismatch on tamper pin 2. */
+#define LDD_DRY_TAMPER_PIN_3 0x00080000U /*!< Mismatch on tamper pin 3. */
+#define LDD_DRY_TAMPER_PIN_4 0x00100000U /*!< Mismatch on tamper pin 4. */
+#define LDD_DRY_TAMPER_PIN_5 0x00200000U /*!< Mismatch on tamper pin 5. */
+#define LDD_DRY_TAMPER_PIN_6 0x00400000U /*!< Mismatch on tamper pin 6. */
+#define LDD_DRY_TAMPER_PIN_7 0x00800000U /*!< Mismatch on tamper pin 7. */
+
+#define LDD_DRY_SECURE_KEY_WORD_0 0x01U /*!< Secure key word 0 mask */
+#define LDD_DRY_SECURE_KEY_WORD_1 0x02U /*!< Secure key word 1 mask */
+#define LDD_DRY_SECURE_KEY_WORD_2 0x04U /*!< Secure key word 2 mask */
+#define LDD_DRY_SECURE_KEY_WORD_3 0x08U /*!< Secure key word 3 mask */
+#define LDD_DRY_SECURE_KEY_WORD_4 0x10U /*!< Secure key word 4 mask */
+#define LDD_DRY_SECURE_KEY_WORD_5 0x20U /*!< Secure key word 5 mask */
+#define LDD_DRY_SECURE_KEY_WORD_6 0x40U /*!< Secure key word 6 mask */
+#define LDD_DRY_SECURE_KEY_WORD_7 0x80U /*!< Secure key word 7 mask */
+
+/*
+** ===================================================================
+** NFC device types and constants
+** ===================================================================
+*/
+
+/* Events' masks */
+#define LDD_NFC_ON_CMD_ERROR 0x01U /*!< OnCmdError event mask */
+#define LDD_NFC_ON_CMD_DONE 0x02U /*!< OnCmdDone event mask */
+
+/* Pins' masks */
+#define LDD_NFC_CE0_PIN 0x01U /*!< CE0 pin mask */
+#define LDD_NFC_RB0_PIN 0x02U /*!< RB0 pin mask */
+#define LDD_NFC_CE1_PIN 0x04U /*!< CE1 pin mask */
+#define LDD_NFC_RB1_PIN 0x08U /*!< RB1 pin mask */
+#define LDD_NFC_CE2_PIN 0x10U /*!< CE2 pin mask */
+#define LDD_NFC_RB2_PIN 0x20U /*!< RB2 pin mask */
+#define LDD_NFC_CE3_PIN 0x40U /*!< CE3 pin mask */
+#define LDD_NFC_RB3_PIN 0x80U /*!< RB3 pin mask */
+#define LDD_NFC_ALE_PIN 0x0100U /*!< ALE pin mask */
+#define LDD_NFC_CLE_PIN 0x0200U /*!< CLE pin mask */
+#define LDD_NFC_RE_PIN 0x0400U /*!< RE pin mask */
+#define LDD_NFC_WE_PIN 0x0800U /*!< WE pin mask */
+#define LDD_NFC_D0_PIN 0x00010000U /*!< D0 pin mask */
+#define LDD_NFC_D1_PIN 0x00020000U /*!< D1 pin mask */
+#define LDD_NFC_D2_PIN 0x00040000U /*!< D2 pin mask */
+#define LDD_NFC_D3_PIN 0x00080000U /*!< D3 pin mask */
+#define LDD_NFC_D4_PIN 0x00100000U /*!< D4 pin mask */
+#define LDD_NFC_D5_PIN 0x00200000U /*!< D5 pin mask */
+#define LDD_NFC_D6_PIN 0x00400000U /*!< D6 pin mask */
+#define LDD_NFC_D7_PIN 0x00800000U /*!< D7 pin mask */
+#define LDD_NFC_D8_PIN 0x01000000U /*!< D8 pin mask */
+#define LDD_NFC_D9_PIN 0x02000000U /*!< D9 pin mask */
+#define LDD_NFC_D10_PIN 0x04000000U /*!< D10 pin mask */
+#define LDD_NFC_D11_PIN 0x08000000U /*!< D11 pin mask */
+#define LDD_NFC_D12_PIN 0x10000000U /*!< D12 pin mask */
+#define LDD_NFC_D13_PIN 0x20000000U /*!< D13 pin mask */
+#define LDD_NFC_D14_PIN 0x40000000U /*!< D14 pin mask */
+#define LDD_NFC_D15_PIN 0x80000000U /*!< D15 pin mask */
+
+typedef uint32_t LDD_NFC_TTargetID; /*!< NFC target ID type */
+
+/*! NCF command codes */
+typedef enum {
+ LDD_NFC_CMD_NONE = 0x00U, /* No command */
+ LDD_NFC_CMD_RESET = 0x01U, /* Reset command */
+ LDD_NFC_CMD_ERASE = 0x02U, /* Erase command */
+ LDD_NFC_CMD_READ_ID = 0x03U, /* Read ID command */
+ LDD_NFC_CMD_READ_PAGES = 0x04U, /* Read pages command */
+ LDD_NFC_CMD_WRITE_PAGES = 0x05U, /* Write pages command */
+ LDD_NFC_CMD_ERASE_BLOCKS = 0x06U, /* Erase page command */
+ LDD_NFC_CMD_READ_RAW_PAGE = 0x07U, /* Read raw page command */
+ LDD_NFC_CMD_WRITE_RAW_PAGE = 0x08U /* Write raw page command */
+} LDD_NFC_TeCmd;
+
+/*
+** ===================================================================
+** LCDC device types and constants
+** ===================================================================
+*/
+
+#define LDD_LCDC_ON_ERROR 0x01U /*!< OnError event mask */
+#define LDD_LCDC_ON_START_OF_FRAME 0x02U /*!< OnStartOfFrame event mask */
+#define LDD_LCDC_ON_END_OF_FRAME 0x04U /*!< OnEndOfFrame event mask */
+
+#define LDD_LCDC_NO_ERR 0x00U /*!< No error */
+#define LDD_LCDC_PLANE_0_UNDERRUN_ERR 0x01U /*!< Plane 0 underrurn error */
+#define LDD_LCDC_PLANE_1_UNDERRUN_ERR 0x02U /*!< Plane 1 underrurn error */
+
+#define LDD_LCDC_REVERSED_VERTICAL_SCAN 0x8000U /*!< Enable reversed vertical scan (flip along x-axis) */
+
+/*! Bitmap description */
+typedef struct {
+ LDD_TData *Address; /*!< Bitmap starting address */
+ uint16_t Width; /*!< Bitmap width */
+ uint16_t Height; /*!< Bitmap height */
+ uint16_t Format; /*!< Bitmap format */
+} LDD_LCDC_TBitmap;
+
+/*! Window description */
+typedef struct {
+ uint16_t X; /*!< Window position in bitmap - X */
+ uint16_t Y; /*!< Window position in bitmap - Y */
+ uint16_t Width; /*!< Window width */
+ uint16_t Height; /*!< Window height */
+} LDD_LCDC_TWindow;
+
+/*! Cursor type */
+typedef enum {
+ LDD_LCDC_DISABLED = 0, /*!< Cursor disabled */
+ LDD_LCDC_ALWAYS_1, /*!< Cursor 1''s, monochrome display only. */
+ LDD_LCDC_ALWAYS_0, /*!< Cursor 0''s, monochrome display only. */
+ LDD_LCDC_COLOR, /*!< Defined cursor color, color display only. */
+ LDD_LCDC_INVERTED, /*!< Inverted background, monochrome display only. */
+ LDD_LCDC_INVERTED_COLOR, /*!< Inverted cursor color, color display only. */
+ LDD_LCDC_AND, /*!< Cursor color AND backgroun, color display only. */
+ LDD_LCDC_OR, /*!< Cursor color OR backgroun, color display only. */
+ LDD_LCDC_XOR
+} LDD_LCDC_CursorOperation;
+
+/*! Plane identification */
+typedef enum {
+ LDD_LCDC_PLANE_COMMON, /*!< Common for all planes */
+ LDD_LCDC_PLANE_0, /*!< Plane (layer) 0 */
+ LDD_LCDC_PLANE_1 /*!< Plane (layer) 1 */
+} LDD_LCDC_TPlaneID;
+
+
+/*
+** ===================================================================
+** Interrupt vector constants
+** ===================================================================
+*/
+#define LDD_ivIndex_INT_Initial_Stack_Pointer 0x00u
+#define LDD_ivIndex_INT_Initial_Program_Counter 0x01u
+#define LDD_ivIndex_INT_NMI 0x02u
+#define LDD_ivIndex_INT_Hard_Fault 0x03u
+#define LDD_ivIndex_INT_Mem_Manage_Fault 0x04u
+#define LDD_ivIndex_INT_Bus_Fault 0x05u
+#define LDD_ivIndex_INT_Usage_Fault 0x06u
+#define LDD_ivIndex_INT_Reserved7 0x07u
+#define LDD_ivIndex_INT_Reserved8 0x08u
+#define LDD_ivIndex_INT_Reserved9 0x09u
+#define LDD_ivIndex_INT_Reserved10 0x0Au
+#define LDD_ivIndex_INT_SVCall 0x0Bu
+#define LDD_ivIndex_INT_DebugMonitor 0x0Cu
+#define LDD_ivIndex_INT_Reserved13 0x0Du
+#define LDD_ivIndex_INT_PendableSrvReq 0x0Eu
+#define LDD_ivIndex_INT_SysTick 0x0Fu
+#define LDD_ivIndex_INT_DMA0_DMA16 0x10u
+#define LDD_ivIndex_INT_DMA1_DMA17 0x11u
+#define LDD_ivIndex_INT_DMA2_DMA18 0x12u
+#define LDD_ivIndex_INT_DMA3_DMA19 0x13u
+#define LDD_ivIndex_INT_DMA4_DMA20 0x14u
+#define LDD_ivIndex_INT_DMA5_DMA21 0x15u
+#define LDD_ivIndex_INT_DMA6_DMA22 0x16u
+#define LDD_ivIndex_INT_DMA7_DMA23 0x17u
+#define LDD_ivIndex_INT_DMA8_DMA24 0x18u
+#define LDD_ivIndex_INT_DMA9_DMA25 0x19u
+#define LDD_ivIndex_INT_DMA10_DMA26 0x1Au
+#define LDD_ivIndex_INT_DMA11_DMA27 0x1Bu
+#define LDD_ivIndex_INT_DMA12_DMA28 0x1Cu
+#define LDD_ivIndex_INT_DMA13_DMA29 0x1Du
+#define LDD_ivIndex_INT_DMA14_DMA30 0x1Eu
+#define LDD_ivIndex_INT_DMA15_DMA31 0x1Fu
+#define LDD_ivIndex_INT_DMA_Error 0x20u
+#define LDD_ivIndex_INT_MCM 0x21u
+#define LDD_ivIndex_INT_FTFE 0x22u
+#define LDD_ivIndex_INT_Read_Collision 0x23u
+#define LDD_ivIndex_INT_LVD_LVW 0x24u
+#define LDD_ivIndex_INT_LLW 0x25u
+#define LDD_ivIndex_INT_Watchdog 0x26u
+#define LDD_ivIndex_INT_RNG 0x27u
+#define LDD_ivIndex_INT_I2C0 0x28u
+#define LDD_ivIndex_INT_I2C1 0x29u
+#define LDD_ivIndex_INT_SPI0 0x2Au
+#define LDD_ivIndex_INT_SPI1 0x2Bu
+#define LDD_ivIndex_INT_SPI2 0x2Cu
+#define LDD_ivIndex_INT_CAN0_ORed_Message_buffer 0x2Du
+#define LDD_ivIndex_INT_CAN0_Bus_Off 0x2Eu
+#define LDD_ivIndex_INT_CAN0_Error 0x2Fu
+#define LDD_ivIndex_INT_CAN0_Tx_Warning 0x30u
+#define LDD_ivIndex_INT_CAN0_Rx_Warning 0x31u
+#define LDD_ivIndex_INT_CAN0_Wake_Up 0x32u
+#define LDD_ivIndex_INT_I2S0_Tx 0x33u
+#define LDD_ivIndex_INT_I2S0_Rx 0x34u
+#define LDD_ivIndex_INT_CAN1_ORed_Message_buffer 0x35u
+#define LDD_ivIndex_INT_CAN1_Bus_Off 0x36u
+#define LDD_ivIndex_INT_CAN1_Error 0x37u
+#define LDD_ivIndex_INT_CAN1_Tx_Warning 0x38u
+#define LDD_ivIndex_INT_CAN1_Rx_Warning 0x39u
+#define LDD_ivIndex_INT_CAN1_Wake_Up 0x3Au
+#define LDD_ivIndex_INT_Reserved59 0x3Bu
+#define LDD_ivIndex_INT_UART0_LON 0x3Cu
+#define LDD_ivIndex_INT_UART0_RX_TX 0x3Du
+#define LDD_ivIndex_INT_UART0_ERR 0x3Eu
+#define LDD_ivIndex_INT_UART1_RX_TX 0x3Fu
+#define LDD_ivIndex_INT_UART1_ERR 0x40u
+#define LDD_ivIndex_INT_UART2_RX_TX 0x41u
+#define LDD_ivIndex_INT_UART2_ERR 0x42u
+#define LDD_ivIndex_INT_UART3_RX_TX 0x43u
+#define LDD_ivIndex_INT_UART3_ERR 0x44u
+#define LDD_ivIndex_INT_UART4_RX_TX 0x45u
+#define LDD_ivIndex_INT_UART4_ERR 0x46u
+#define LDD_ivIndex_INT_UART5_RX_TX 0x47u
+#define LDD_ivIndex_INT_UART5_ERR 0x48u
+#define LDD_ivIndex_INT_ADC0 0x49u
+#define LDD_ivIndex_INT_ADC1 0x4Au
+#define LDD_ivIndex_INT_CMP0 0x4Bu
+#define LDD_ivIndex_INT_CMP1 0x4Cu
+#define LDD_ivIndex_INT_CMP2 0x4Du
+#define LDD_ivIndex_INT_FTM0 0x4Eu
+#define LDD_ivIndex_INT_FTM1 0x4Fu
+#define LDD_ivIndex_INT_FTM2 0x50u
+#define LDD_ivIndex_INT_CMT 0x51u
+#define LDD_ivIndex_INT_RTC 0x52u
+#define LDD_ivIndex_INT_RTC_Seconds 0x53u
+#define LDD_ivIndex_INT_PIT0 0x54u
+#define LDD_ivIndex_INT_PIT1 0x55u
+#define LDD_ivIndex_INT_PIT2 0x56u
+#define LDD_ivIndex_INT_PIT3 0x57u
+#define LDD_ivIndex_INT_PDB0 0x58u
+#define LDD_ivIndex_INT_USB0 0x59u
+#define LDD_ivIndex_INT_USBDCD 0x5Au
+#define LDD_ivIndex_INT_ENET_1588_Timer 0x5Bu
+#define LDD_ivIndex_INT_ENET_Transmit 0x5Cu
+#define LDD_ivIndex_INT_ENET_Receive 0x5Du
+#define LDD_ivIndex_INT_ENET_Error 0x5Eu
+#define LDD_ivIndex_INT_Reserved95 0x5Fu
+#define LDD_ivIndex_INT_SDHC 0x60u
+#define LDD_ivIndex_INT_DAC0 0x61u
+#define LDD_ivIndex_INT_DAC1 0x62u
+#define LDD_ivIndex_INT_TSI0 0x63u
+#define LDD_ivIndex_INT_MCG 0x64u
+#define LDD_ivIndex_INT_LPTimer 0x65u
+#define LDD_ivIndex_INT_Reserved102 0x66u
+#define LDD_ivIndex_INT_PORTA 0x67u
+#define LDD_ivIndex_INT_PORTB 0x68u
+#define LDD_ivIndex_INT_PORTC 0x69u
+#define LDD_ivIndex_INT_PORTD 0x6Au
+#define LDD_ivIndex_INT_PORTE 0x6Bu
+#define LDD_ivIndex_INT_PORTF 0x6Cu
+#define LDD_ivIndex_INT_DDR 0x6Du
+#define LDD_ivIndex_INT_SWI 0x6Eu
+#define LDD_ivIndex_INT_NFC 0x6Fu
+#define LDD_ivIndex_INT_USBHS 0x70u
+#define LDD_ivIndex_INT_LCD 0x71u
+#define LDD_ivIndex_INT_CMP3 0x72u
+#define LDD_ivIndex_INT_Reserved115 0x73u
+#define LDD_ivIndex_INT_Reserved116 0x74u
+#define LDD_ivIndex_INT_FTM3 0x75u
+#define LDD_ivIndex_INT_ADC2 0x76u
+#define LDD_ivIndex_INT_ADC3 0x77u
+#define LDD_ivIndex_INT_I2S1_Tx 0x78u
+#define LDD_ivIndex_INT_I2S1_Rx 0x79u
+
+#endif /* __PE_Types_H */
+
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Generated_Code/Vectors.c b/Generated_Code/Vectors.c
new file mode 100644
index 0000000000000000000000000000000000000000..4383846e2acbbdd1f98c0e9d4ef6e4192e6ea887
--- /dev/null
+++ b/Generated_Code/Vectors.c
@@ -0,0 +1,214 @@
+/** ###################################################################
+** This component module is generated by Processor Expert. Do not modify it.
+** Filename : Vectors.c
+** Project : Lab1
+** Processor : MK70FN1M0VMJ12
+** Version : Component 01.028, Driver 01.04, CPU db: 3.00.000
+** Repository : Kinetis
+** Compiler : GNU C Compiler
+** Date/Time : 2015-07-29, 13:56, # CodeGen: 10
+** Abstract :
+**
+** Settings :
+**
+**
+** Copyright : 1997 - 2015 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+** ###################################################################*/
+/*!
+** @file Vectors.c
+** @version 01.04
+** @brief
+**
+*/
+/*!
+** @addtogroup Vectors_module Vectors module documentation
+** @{
+*/
+
+#include "Cpu.h"
+#include "timer.h"
+#include "buttons.h"
+
+ /* ISR prototype */
+ extern uint32_t __SP_INIT;
+ extern
+ #ifdef __cplusplus
+ "C"
+ #endif
+ void __thumb_startup( void );
+
+
+ /*lint -esym(765,__vect_table) Disable MISRA rule (8.10) checking for symbols (__vect_table). Definition of the interrupt vector table placed by linker on a predefined location. */
+ /*lint -save -e926 -e927 -e928 -e929 Disable MISRA rule (11.4) checking. Need to explicitly cast pointers to the general ISR for Interrupt vector table */
+
+ __attribute__ ((section (".vectortable"))) const tVectorTable __vect_table = { /* Interrupt vector table */
+
+ /* ISR name No. Address Pri Name Description */
+ &__SP_INIT, /* 0x00 0x00000000 - ivINT_Initial_Stack_Pointer used by PE */
+ {
+ (tIsrFunc)&__thumb_startup, /* 0x01 0x00000004 - ivINT_Initial_Program_Counter used by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x02 0x00000008 -2 ivINT_NMI unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x03 0x0000000C -1 ivINT_Hard_Fault unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x04 0x00000010 - ivINT_Mem_Manage_Fault unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x05 0x00000014 - ivINT_Bus_Fault unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x06 0x00000018 - ivINT_Usage_Fault unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x07 0x0000001C - ivINT_Reserved7 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x08 0x00000020 - ivINT_Reserved8 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x09 0x00000024 - ivINT_Reserved9 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x0A 0x00000028 - ivINT_Reserved10 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x0B 0x0000002C - ivINT_SVCall unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x0C 0x00000030 - ivINT_DebugMonitor unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x0D 0x00000034 - ivINT_Reserved13 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x0E 0x00000038 - ivINT_PendableSrvReq unused by PE */
+ (tIsrFunc)&Timer_TickISR, /* 0x0F 0x0000003C - ivINT_SysTick unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x10 0x00000040 - ivINT_DMA0_DMA16 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x11 0x00000044 - ivINT_DMA1_DMA17 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x12 0x00000048 - ivINT_DMA2_DMA18 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x13 0x0000004C - ivINT_DMA3_DMA19 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x14 0x00000050 - ivINT_DMA4_DMA20 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x15 0x00000054 - ivINT_DMA5_DMA21 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x16 0x00000058 - ivINT_DMA6_DMA22 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x17 0x0000005C - ivINT_DMA7_DMA23 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x18 0x00000060 - ivINT_DMA8_DMA24 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x19 0x00000064 - ivINT_DMA9_DMA25 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1A 0x00000068 - ivINT_DMA10_DMA26 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1B 0x0000006C - ivINT_DMA11_DMA27 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1C 0x00000070 - ivINT_DMA12_DMA28 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1D 0x00000074 - ivINT_DMA13_DMA29 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1E 0x00000078 - ivINT_DMA14_DMA30 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x1F 0x0000007C - ivINT_DMA15_DMA31 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x20 0x00000080 - ivINT_DMA_Error unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x21 0x00000084 - ivINT_MCM unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x22 0x00000088 - ivINT_FTFE unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x23 0x0000008C - ivINT_Read_Collision unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x24 0x00000090 - ivINT_LVD_LVW unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x25 0x00000094 - ivINT_LLW unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x26 0x00000098 - ivINT_Watchdog unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x27 0x0000009C - ivINT_RNG unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x28 0x000000A0 - ivINT_I2C0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x29 0x000000A4 - ivINT_I2C1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2A 0x000000A8 - ivINT_SPI0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2B 0x000000AC - ivINT_SPI1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2C 0x000000B0 - ivINT_SPI2 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2D 0x000000B4 - ivINT_CAN0_ORed_Message_buffer unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2E 0x000000B8 - ivINT_CAN0_Bus_Off unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x2F 0x000000BC - ivINT_CAN0_Error unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x30 0x000000C0 - ivINT_CAN0_Tx_Warning unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x31 0x000000C4 - ivINT_CAN0_Rx_Warning unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x32 0x000000C8 - ivINT_CAN0_Wake_Up unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x33 0x000000CC - ivINT_I2S0_Tx unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x34 0x000000D0 - ivINT_I2S0_Rx unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x35 0x000000D4 - ivINT_CAN1_ORed_Message_buffer unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x36 0x000000D8 - ivINT_CAN1_Bus_Off unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x37 0x000000DC - ivINT_CAN1_Error unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x38 0x000000E0 - ivINT_CAN1_Tx_Warning unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x39 0x000000E4 - ivINT_CAN1_Rx_Warning unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3A 0x000000E8 - ivINT_CAN1_Wake_Up unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3B 0x000000EC - ivINT_Reserved59 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3C 0x000000F0 - ivINT_UART0_LON unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3D 0x000000F4 - ivINT_UART0_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3E 0x000000F8 - ivINT_UART0_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x3F 0x000000FC - ivINT_UART1_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x40 0x00000100 - ivINT_UART1_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x41 0x00000104 - ivINT_UART2_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x42 0x00000108 - ivINT_UART2_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x43 0x0000010C - ivINT_UART3_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x44 0x00000110 - ivINT_UART3_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x45 0x00000114 - ivINT_UART4_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x46 0x00000118 - ivINT_UART4_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x47 0x0000011C - ivINT_UART5_RX_TX unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x48 0x00000120 - ivINT_UART5_ERR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x49 0x00000124 - ivINT_ADC0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4A 0x00000128 - ivINT_ADC1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4B 0x0000012C - ivINT_CMP0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4C 0x00000130 - ivINT_CMP1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4D 0x00000134 - ivINT_CMP2 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4E 0x00000138 - ivINT_FTM0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x4F 0x0000013C - ivINT_FTM1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x50 0x00000140 - ivINT_FTM2 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x51 0x00000144 - ivINT_CMT unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x52 0x00000148 - ivINT_RTC unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x53 0x0000014C - ivINT_RTC_Seconds unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x54 0x00000150 - ivINT_PIT0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x55 0x00000154 - ivINT_PIT1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x56 0x00000158 - ivINT_PIT2 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x57 0x0000015C - ivINT_PIT3 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x58 0x00000160 - ivINT_PDB0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x59 0x00000164 - ivINT_USB0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5A 0x00000168 - ivINT_USBDCD unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5B 0x0000016C - ivINT_ENET_1588_Timer unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5C 0x00000170 - ivINT_ENET_Transmit unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5D 0x00000174 - ivINT_ENET_Receive unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5E 0x00000178 - ivINT_ENET_Error unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x5F 0x0000017C - ivINT_Reserved95 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x60 0x00000180 - ivINT_SDHC unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x61 0x00000184 - ivINT_DAC0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x62 0x00000188 - ivINT_DAC1 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x63 0x0000018C - ivINT_TSI0 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x64 0x00000190 - ivINT_MCG unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x65 0x00000194 - ivINT_LPTimer unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x66 0x00000198 - ivINT_Reserved102 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x67 0x0000019C - ivINT_PORTA unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x68 0x000001A0 - ivINT_PORTB unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x69 0x000001A4 - ivINT_PORTC unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x6A 0x000001A8 - ivINT_PORTD unused by PE */
+ (tIsrFunc)&PortE_ISR, /* 0x6B 0x000001AC - ivINT_PORTE unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x6C 0x000001B0 - ivINT_PORTF unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x6D 0x000001B4 - ivINT_DDR unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x6E 0x000001B8 - ivINT_SWI unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x6F 0x000001BC - ivINT_NFC unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x70 0x000001C0 - ivINT_USBHS unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x71 0x000001C4 - ivINT_LCD unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x72 0x000001C8 - ivINT_CMP3 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x73 0x000001CC - ivINT_Reserved115 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x74 0x000001D0 - ivINT_Reserved116 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x75 0x000001D4 - ivINT_FTM3 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x76 0x000001D8 - ivINT_ADC2 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x77 0x000001DC - ivINT_ADC3 unused by PE */
+ (tIsrFunc)&Cpu_Interrupt, /* 0x78 0x000001E0 - ivINT_I2S1_Tx unused by PE */
+ (tIsrFunc)&Cpu_Interrupt /* 0x79 0x000001E4 - ivINT_I2S1_Rx unused by PE */
+ }
+ };
+ /*lint -restore Enable MISRA rule (11.4) checking. */
+
+
+/*!
+** @}
+*/
+/*
+** ###################################################################
+**
+** This file was created by Processor Expert 10.5 [05.21]
+** for the Freescale Kinetis series of microcontrollers.
+**
+** ###################################################################
+*/
diff --git a/Library/LEDs.h b/Library/LEDs.h
new file mode 100644
index 0000000000000000000000000000000000000000..591b080cb2137f4039429f354001a6bb603341d0
--- /dev/null
+++ b/Library/LEDs.h
@@ -0,0 +1,55 @@
+/*! @file
+ *
+ * @brief Routines to access the LEDs on the TWR-K70F120M.
+ *
+ * This contains the functions for operating the LEDs.
+ *
+ * @author PMcL
+ * @date 2015-08-15
+ */
+
+#ifndef LEDS_H
+#define LEDS_H
+
+// new types
+#include "types.h"
+
+/*! @brief LED to pin mapping on the TWR-K70F120M
+ *
+ */
+typedef enum
+{
+ LED_ORANGE = (1 << 11),
+ LED_YELLOW = (1 << 28),
+ LED_GREEN = (1 << 29),
+ LED_BLUE = (1 << 10)
+} TLED;
+
+/*! @brief Sets up the LEDs before first use.
+ *
+ * @return bool - TRUE if the LEDs were successfully initialized.
+ */
+bool LEDs_Init(void);
+
+/*! @brief Turns an LED on.
+ *
+ * @param color The color of the LED to turn on.
+ * @note Assumes that LEDs_Init has been called.
+ */
+void LEDs_On(const TLED color);
+
+/*! @brief Turns off an LED.
+ *
+ * @param color THe color of the LED to turn off.
+ * @note Assumes that LEDs_Init has been called.
+ */
+void LEDs_Off(const TLED color);
+
+/*! @brief Toggles an LED.
+ *
+ * @param color THe color of the LED to toggle.
+ * @note Assumes that LEDs_Init has been called.
+ */
+void LEDs_Toggle(const TLED color);
+
+#endif
diff --git a/Library/buttons.h b/Library/buttons.h
new file mode 100644
index 0000000000000000000000000000000000000000..e3a7476b0a42ada039d6c23247e0decd125d6ce2
--- /dev/null
+++ b/Library/buttons.h
@@ -0,0 +1,40 @@
+/*! @file
+ *
+ * @brief HAL for pushbutton switches on the TWR-K70.
+ *
+ * This contains the functions for the pushbutton switches on the TWR-K70.
+*
+ * @author PMcL
+ * @date 2015-10-25
+ */
+
+#ifndef BUTTONS_H
+#define BUTTONS_H
+
+// New types
+#include "types.h"
+
+/*! @brief Initializes the pushbutton switches.
+ *
+ * @param buttonSetup is a pointer to a switch setup structure.
+ * @param userFunction is a pointer to a user callback function.
+ */
+bool Buttons_Init(void (*userFunction)(void));
+
+/*! @brief Interrupt service routine for Port D buttons.
+ *
+ * A button in Port D has been pressed.
+ * The user callback function will be called.
+ * @note Assumes the button has been initialized.
+ */
+void __attribute__ ((interrupt)) PortD_ISR(void);
+
+/*! @brief Interrupt service routine for Port E buttons.
+ *
+ * A button in Port E has been pressed.
+ * The user callback function will be called.
+ * @note Assumes the button has been initialized.
+ */
+void __attribute__ ((interrupt)) PortE_ISR(void);
+
+#endif
diff --git a/Library/libLab0.a b/Library/libLab0.a
new file mode 100644
index 0000000000000000000000000000000000000000..88e3c5660faba329560ce247c598246a0cec6db5
Binary files /dev/null and b/Library/libLab0.a differ
diff --git a/Library/timer.h b/Library/timer.h
new file mode 100644
index 0000000000000000000000000000000000000000..5458d7d0f09457011e50ab648395492e43ac169b
--- /dev/null
+++ b/Library/timer.h
@@ -0,0 +1,33 @@
+/*! @file
+ *
+ * @brief Routines to implement packet encoding and decoding for the serial port.
+ *
+ * This contains the functions for implementing the "Tower to PC Protocol" 5-byte packets.
+ *
+ * @author PMcL
+ * @date 2015-07-23
+ */
+
+#ifndef TIMER_H
+#define TIMER_H
+
+// new types
+#include "types.h"
+
+/*! @brief Initializes the Timer before first use.
+ *
+ * Sets up the internal SysTick clock.
+ * Registers the user's callback function.
+ * @param userFunction is a pointer to a user callback function.
+ */
+void Timer_Init(void (*userFunction)(void));
+
+/*! @brief Interrupt service routine for the timer.
+ *
+ * The internal systick clock has ticked.
+ * The user callback function will be called after 1 second has elapsed.
+ * @note Assumes the Timer has been initialized.
+ */
+void __attribute__ ((interrupt)) Timer_TickISR(void);
+
+#endif
diff --git a/Library/types.h b/Library/types.h
new file mode 100644
index 0000000000000000000000000000000000000000..1341ab97cba24ebf4d1da989cf90118eaffef941
--- /dev/null
+++ b/Library/types.h
@@ -0,0 +1,60 @@
+/*! @file
+ *
+ * @brief Declares new types.
+ *
+ * This contains types that are especially useful for the Tower to PC Protocol.
+ *
+ * @author PMcL
+ * @date 2015-07-23
+ */
+
+#ifndef TYPES_H
+#define TYPES_H
+
+#include
+#include
+
+// Unions to efficiently access hi and lo parts of integers and words
+typedef union
+{
+ int16_t l;
+ struct
+ {
+ int8_t Lo;
+ int8_t Hi;
+ } s;
+} int16union_t;
+
+typedef union
+{
+ uint16_t l;
+ struct
+ {
+ uint8_t Lo;
+ uint8_t Hi;
+ } s;
+} uint16union_t;
+
+// Union to efficiently access hi and lo parts of a long integer
+typedef union
+{
+ uint32_t l;
+ struct
+ {
+ uint16_t Lo;
+ uint16_t Hi;
+ } s;
+} uint32union_t;
+
+// Union to efficiently access individual bytes of a float
+typedef union
+{
+ float d;
+ struct
+ {
+ uint16union_t dLo;
+ uint16union_t dHi;
+ } dParts;
+} TFloat;
+
+#endif
diff --git a/ProcessorExpert.pe b/ProcessorExpert.pe
new file mode 100644
index 0000000000000000000000000000000000000000..f5408dec9f0814ca0a587ea546ace2a445c01f95
--- /dev/null
+++ b/ProcessorExpert.pe
@@ -0,0 +1,39543 @@
+
+
+
+ Lab0
+ PMcL
+ 7
+ 2015-07-20
+ Eclipse IDE
+ 1.12.0.RT7_b1515-0427
+
+
+ main
+ Sources
+ Generated_Code
+ Documentation
+
+ Project_Settings
+ Static_Code
+
+ 3
+ 3
+ 3
+ true
+ false
+ true
+ 0
+ false
+ false
+ true
+ false
+ true
+ 6
+ true
+ false
+ true
+ CLASSIC
+ true
+ true
+ false
+
+ STANDALONE
+
+
+ file:/${ProcessorExpert_loc}/Repositories/Kinetis_Repository
+ com.freescale.processorexpert.processor.mk70fn1m0mj15
+ MK70FN1M0MJ15
+ Cpu
+ 2
+ false
+ ALWAYS_WRITE
+ CPU_CHIP2
+
+
+
+ 01.028
+ false
+
+
+ DeviceName
+ false
+ false
+ Cpu
+
+
+ CPU
+ false
+ false
+ MK70FN1M0VMJ12
+
+
+ SharedInternalProperties
+ 1
+
+
+ SharedInternalPropertiesGrp
+ false
+ false
+ false
+
+
+ CPU_peripheral
+ false
+ false
+ CPU
+ false
+
+
+ MemModelDev
+ false
+ false
+ MemModel_NoFlexMem
+ false
+
+
+ Shared_ClockSettings
+ 1
+
+
+ ClockSettingGrp
+ false
+ false
+ false
+
+
+ ICLK
+ false
+ false
+ true
+
+
+ IntOsc
+ false
+ false
+ false
+ 32.768
+
+
+ InitializeSlowTRIM
+ false
+ false
+ false
+ false
+ false
+
+
+ SlowTRIMvalueAddress
+ false
+ false
+ false
+ 1023
+ HEX
+
+
+
+ SlowFTRIMvalueAddress
+ false
+ false
+ false
+ 1022
+ HEX
+
+
+
+ IntOscFast
+ false
+ false
+ false
+ 4
+
+
+ InitializeFastTRIM
+ false
+ false
+ false
+ false
+ false
+
+
+ FastTRIMvalueAddress
+ false
+ false
+ false
+ 1022
+ HEX
+
+
+
+ RTCOSCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ RTCOSC
+ false
+ false
+ false
+ 0.032768
+
+
+ RTCOSC_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ SystemOSCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SystemOSCSrc
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSCExtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSCExtalPin
+
+ false
+
+
+ SystemOSCExtalPinSignal
+ false
+ false
+
+
+
+ SystemOSCXtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSCXtalPin
+
+ false
+
+
+ SystemOSCXtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC
+ false
+ false
+ false
+ 8
+
+
+ SystemOSC_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ExtOscOperatingMode
+ false
+ false
+ false
+ 1
+ 0
+
+
+ SystemOSC1Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ SystemOSC1Src
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSC1Extal_Grp
+ false
+ false
+ true
+
+
+ SystemOSC1ExtalPin
+
+ false
+
+
+ SystemOSC1ExtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC1Xtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSC1XtalPin
+
+ false
+
+
+ SystemOSC1XtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC1
+ false
+ false
+ false
+ 8
+
+
+ SystemOSC1_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ExtOsc1OperatingMode
+ false
+ false
+ false
+ 1
+ 0
+
+
+ CLKModeList
+ false
+ 1
+ false
+ true
+
+
+ CLKMode0
+ false
+ false
+ true
+
+
+ IRCLKGrp0
+ false
+ false
+ false
+
+
+ IRCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ IREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ IRCLKSelectCLKMode0
+ false
+ false
+ false
+ 0
+ false
+
+
+ FCRDIVCLKMode0
+ false
+ true
+ 1
+ 1
+
+
+ IRCLKClkCLKMode0
+ false
+ 0.032768
+
+
+ ERCLKGrp0
+ false
+ false
+ false
+
+
+ SystemOSCERCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSCEREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ ERCLKClkCLKMode0
+ false
+ 0
+
+
+ SystemOSC1ERCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSC1EREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ ERCLK1ClkCLKMode0
+ false
+ 0
+
+
+ ERCLK32KSelectCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ERCLK32KClkCLKMode0
+ false
+ 0
+
+
+ MCGGrp0
+ false
+ false
+ true
+
+
+ MCGModeSelCLKMode0
+ false
+ false
+ false
+ 0
+
+
+ PLLCSCLKMode0
+ false
+ false
+ false
+ true
+ 0
+ 0
+
+
+ MCGOUTSelectCLKMode0
+ false
+ 0
+ FLLOUT
+
+
+ MCGModeCLKMode0
+
+
+
+ MCGOutputCLKMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ MCG_ERCLKSelectCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ MCG_ERCLKClkCLKMode0
+ false
+ 0
+
+
+ ClockMonitorGrp0
+ false
+ false
+ true
+
+
+ MCGCMECLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ MCGCME1CLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ MCGCME2CLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ FLLGrp0
+ false
+ false
+ true
+
+
+ FLLEnblCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ FLLOutputCLKMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ FLLFixedClkCLKMode0
+ false
+ 16.384
+
+
+ FLL_RefClkSrcCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ MCG_FRDIV_CLKMode0
+ false
+ false
+ false
+ true
+ 0
+ Auto select
+
+
+ FLLRefClkCLKMode0
+ false
+ 32.768
+
+
+ MCG_FLL_MFactor_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLGrp0
+ false
+ false
+ true
+
+
+ PLLEnblCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLREFSELCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ PLLOutputCLKMode0
+ false
+ false
+ false
+ 120
+
+
+ MCG_PRDIV_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLRefClkCLKMode0
+ false
+ 1
+
+
+ MCG_VDIV_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLL_LOLIECLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLL1Grp0
+ false
+ false
+ true
+
+
+ PLLEnbl1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLSTEN1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLOutput1CLKMode0
+ false
+ false
+ false
+ 120
+
+
+ PLLREFSEL1CLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ MCG_PRDIV1_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLRefClk1CLKMode0
+ false
+ 1
+
+
+ MCG_VDIV1_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLL_LOLIE1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ InitPriority
+ false
+ false
+ minimal priority
+
+
+ WDOGDis
+ false
+ false
+ false
+ 0
+ true
+
+
+ Intperiphgrp
+ false
+ false
+ false
+
+
+ SharedADC0
+ 1
+
+
+ ADCGrp
+ false
+ false
+ false
+
+
+ ADCCondGrp
+ false
+ false
+
+
+ ADCAsynchroClock
+ false
+ false
+ false
+ Auto select
+ true
+
+
+ ADC0CondGrp
+ false
+ false
+
+
+ ADC0AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC1CondGrp
+ false
+ false
+
+
+ ADC1AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC2CondGrp
+ false
+ false
+
+
+ ADC2AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC3CondGrp
+ false
+ false
+
+
+ ADC3AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC4CondGrp
+ false
+ false
+
+
+ ADC4AsynchroClock
+ false
+ false
+ false
+ Auto select
+ true
+
+
+ DisNMINMIPin
+ false
+ false
+ TSI0_CH5/PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b
+ false
+
+
+ SharedNMI
+ 1
+
+
+ NMINMIPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ NMINMIPin
+ false
+ false
+ TSI0_CH5/PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b
+ false
+
+
+ NMINMIPinSignal
+ false
+ false
+
+
+
+ SharedNMI0
+ 1
+
+
+ RCMGrp
+ false
+ false
+ false
+ true
+ false
+
+
+ PeriphDeviceRCM
+ false
+ false
+ RCM
+ false
+
+
+ RCMResetPin
+ false
+ false
+ RESET_b
+ false
+
+
+ RCMResetPinSignal
+ false
+ false
+
+
+
+ RCMFilterInStop
+ false
+ false
+ false
+ typeKinetisRCMFilterInStop
+ 0
+ disabled
+
+
+ RCMFilterInRunWait
+ false
+ false
+ false
+ typeKinetisRCMFilterInRunWait
+ 0
+ disabled
+
+
+ RCMFilterWidth
+ false
+ false
+ false
+ 1
+ DEC
+
+
+ RCMInternalUsageGrp
+ false
+ false
+ true
+
+
+ RCMIsInitialized
+ false
+ 0
+ true
+
+
+ SharedJTAG
+ 1
+
+
+ JTAGGrp
+ false
+ false
+ false
+
+
+ JTAGMode
+ false
+ false
+ false
+ 0
+ true
+
+
+ JTAGTDIPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTDIPin
+ false
+ false
+ TSI0_CH2/PTA1/UART0_RX/FTM0_CH6/JTAG_TDI/EZP_DI
+ false
+
+
+ JTAGTDIPinSignal
+ false
+ false
+
+
+
+ JTAGTDOPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTDOPin
+ false
+ false
+ TSI0_CH3/PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO
+ false
+
+
+ JTAGTDOPinSignal
+ false
+ false
+
+
+
+ JTAGTCKPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTCKPin
+ false
+ false
+ TSI0_CH1/PTA0/UART0_CTS_b/UART0_COL_b/FTM0_CH5/JTAG_TCLK/SWD_CLK/EZP_CLK
+ false
+
+
+ JTAGTCKPinSignal
+ false
+ false
+
+
+
+ JTAGTMSPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTMSPin
+ false
+ false
+ TSI0_CH4/PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO
+ false
+
+
+ JTAGTMSPinSignal
+ false
+ false
+
+
+
+ JTAGnTRSTPinEn
+ false
+ false
+ false
+ false
+ false
+
+
+ JTAGnTRSTPin
+ false
+ false
+
+ false
+
+
+ JTAGnTRSTPinSignal
+ false
+ false
+
+
+
+ SharedFlashOrganization
+ 1
+
+
+ FlashMemoryOrgGrp
+ false
+ false
+ true
+
+
+ SharedFLASHGrp
+ 1
+
+
+ FlexNVMCondGrp
+ false
+ false
+
+
+ FlexNVMSettings
+ false
+ false
+ true
+ true
+
+
+ FlexNVMComponentVersion
+ false
+ false
+
+ true
+
+
+ EEEpart
+ false
+ false
+ false
+ true
+ 10
+ 16384
+
+
+ Dpart
+ false
+ false
+ false
+ true
+ 17
+ 512
+
+
+ FlexNVMSize_Txt
+
+ true
+
+
+ DataFlashSize_KB_Txt
+ 0 KB
+ true
+
+
+ FlexNVMPartitionCodeValue
+ false
+ false
+
+ true
+
+
+ EepromSize_Enum
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ EepromSplitFactorCondGrp
+ false
+ false
+ true
+
+
+ EepromSplitFactor
+ false
+ false
+ false
+ true
+ 2
+ 2
+
+
+ EepromBackupSize_KB_Enum
+ false
+ false
+ false
+ true
+ 0
+ 8
+
+
+ DflashSettingsGrp
+ false
+ false
+ true
+ true
+
+
+ DataFlashStart
+ false
+ 268435456
+ true
+ HEX
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+ DataFlashSize
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+ EepromBackupSettingsGrp
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+ EepromBackupStart
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+ EepromBackupSize
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+ EepromDataSettingsGrp
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+ EepromStart
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+ EepromSize
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+ FlexRAM
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+ FlexRAMStart
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+ FlexRAMSize
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+ EEEFeatureIsInitialized
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+ 4
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+ FlashOrgDscrBlock0
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+ FlashOrgDscrBlockAddress0
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+ FlashOrgDscrBlockSize0
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+ FlashOrgDscrBlockWUnitSize0
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+ FlashOrgDscrBlockEUnitSize0
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+ FlashOrgDscrBlockPUnitSize0
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+ FlashOrgDscrBlock1
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+ FlashOrgDscrBlockAddress1
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+ FlashOrgDscrBlockEUnitSize1
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+ FlashOrgDscrBlockPUnitSize1
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+
+ FlashOrgDscrBlock2
+ false
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+ FlashOrgDscrBlockAddress2
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+ FlashOrgDscrBlockSize2
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+ FlashOrgDscrBlockWUnitSize2
+ false
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+ FlashOrgDscrBlockEUnitSize2
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+ FlashOrgDscrBlockPUnitSize2
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+ FlashOrgDscrBlock3
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+ FlashOrgDscrBlockAddress3
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+ FlashOrgDscrBlockSize3
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+ FlashOrgDscrBlockEUnitSize3
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+ FlashOrgDscrBlockPUnitSize3
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+
+ ShrdPFLASHGrp
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+ FMCGrp
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+ PeriphDeviceFMC
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+ FMCProtGrp
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+ FMCMaster0_Grp
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+ FMCMaster0Prefetch
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+ FMCMaster0AccessProtection
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+ FMCMaster2_Grp
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+ FMCMaster2AccessProtection
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+ FMCMaster3_Grp
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+ FMCMaster3Prefetch
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+ FMCMaster3AccessProtection
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+ FMCMaster4AccessProtection
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+ FMCCacheGrp
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+ FMCBank0DCE
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+ FMCBank0ICE
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+ FMCBank0DPE
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+ FMCBank0IPE
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+ PeriphDeviceFTFL_FlashConfig
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+ FTFL_FlashConfigSecurity
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+ FTFL_FlashConfigSecureValue
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+ FTFL_FlashConfigBackdoorKey0
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+ FTFL_FlashConfigBackdoorKey1
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+ FTFL_FlashConfigBackdoorKey2
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+ FTFL_FlashConfigBackdoorKey3
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+ FTFL_FlashConfigBackdoorKey4
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+ FTFL_FlashConfigBackdoorKey5
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+ FTFL_FlashConfigBackdoorKey6
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+ FTFL_FlashConfigBackdoorKey7
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+ FTFL_FlashConfigProtectionSettingsGrp
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+ FTFL_FlashConfigProgramFlashProtectionSettingsGrp
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+ FTFL_FlashConfigProgramFlashProtectionRegionSize
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+ FTFL_FlashConfigP_protection
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+ FTFL_FlashConfigProgramFlashProtectionRegion16
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+ FTFL_FlashConfigProgramFlashProtectionRegion17
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+ FTFL_FlashConfigProgramFlashProtectionRegion18
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+ FTFL_FlashConfigProgramFlashProtectionRegion22
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+ FTFL_FlashConfigProgramFlashProtectionRegion24
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+ FTFL_FlashConfigDataFlashProtectionRegionSize
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+
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+ FTFL_FlashConfigD_protection
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+ FTFL_FlashConfigEepromProtectionRegionSize
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+ FTFL_FlashConfigE_protection
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+ FTFL_FlashConfigEzPortDis
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+ ShrdMPUGrp
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+ PeriphDeviceMPU
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+ MPUValidSetMPU
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+ MPURegionValid0
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+ MPUStartAddress0
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+ MPUEndAddress0
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+ MPUAccCtrlRightsGrp0
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+ MPUMaster1UWAccess0
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+ typeKinetisMPUMaster3UXAccess
+ 1
+ denied
+
+
+ MPUMaster4Grp13
+ false
+ false
+ false
+
+
+ MPUMaster4URAccess13
+ false
+ false
+ false
+ typeKinetisMPUMaster4URAccess
+ 1
+ denied
+
+
+ MPUMaster4UWAccess13
+ false
+ false
+ false
+ typeKinetisMPUMaster4UWAccess
+ 1
+ denied
+
+
+ MPUMaster5Grp13
+ false
+ false
+ false
+
+
+ MPUMaster5URAccess13
+ false
+ false
+ false
+ typeKinetisMPUMaster5URAccess
+ 1
+ denied
+
+
+ MPUMaster5UWAccess13
+ false
+ false
+ false
+ typeKinetisMPUMaster5UWAccess
+ 1
+ denied
+
+
+ MPURegionValid14
+ false
+ false
+ false
+ false
+ false
+
+
+ MPUStartAddress14
+ false
+ false
+ 0
+
+
+ MPUEndAddress14
+ false
+ false
+ 0
+
+
+ MPUAccCtrlRightsGrp14
+ false
+ false
+ false
+
+
+ MPUMaster0Grp14
+ false
+ false
+ false
+
+
+ MPUMaster0SAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster0SAccess
+ 0
+ rwx
+
+
+ MPUMaster0URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster0URAccess
+ 1
+ denied
+
+
+ MPUMaster0UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster0UWAccess
+ 1
+ denied
+
+
+ MPUMaster0UXAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster0UXAccess
+ 1
+ denied
+
+
+ MPUMaster1Grp14
+ false
+ false
+ false
+
+
+ MPUMaster1SAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster1SAccess
+ 0
+ rwx
+
+
+ MPUMaster1URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster1URAccess
+ 1
+ denied
+
+
+ MPUMaster1UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster1UWAccess
+ 1
+ denied
+
+
+ MPUMaster1UXAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster1UXAccess
+ 1
+ denied
+
+
+ MPUMaster2Grp14
+ false
+ false
+ false
+
+
+ MPUMaster2SAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster2SAccess
+ 0
+ rwx
+
+
+ MPUMaster2URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster2URAccess
+ 1
+ denied
+
+
+ MPUMaster2UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster2UWAccess
+ 1
+ denied
+
+
+ MPUMaster2UXAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster2UXAccess
+ 1
+ denied
+
+
+ MPUMaster3Grp14
+ false
+ false
+ false
+
+
+ MPUMaster3SAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster3SAccess
+ 0
+ rwx
+
+
+ MPUMaster3URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster3URAccess
+ 1
+ denied
+
+
+ MPUMaster3UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster3UWAccess
+ 1
+ denied
+
+
+ MPUMaster3UXAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster3UXAccess
+ 1
+ denied
+
+
+ MPUMaster4Grp14
+ false
+ false
+ false
+
+
+ MPUMaster4URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster4URAccess
+ 1
+ denied
+
+
+ MPUMaster4UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster4UWAccess
+ 1
+ denied
+
+
+ MPUMaster5Grp14
+ false
+ false
+ false
+
+
+ MPUMaster5URAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster5URAccess
+ 1
+ denied
+
+
+ MPUMaster5UWAccess14
+ false
+ false
+ false
+ typeKinetisMPUMaster5UWAccess
+ 1
+ denied
+
+
+ MPURegionValid15
+ false
+ false
+ false
+ false
+ false
+
+
+ MPUStartAddress15
+ false
+ false
+ 0
+
+
+ MPUEndAddress15
+ false
+ false
+ 0
+
+
+ MPUAccCtrlRightsGrp15
+ false
+ false
+ false
+
+
+ MPUMaster0Grp15
+ false
+ false
+ false
+
+
+ MPUMaster0SAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster0SAccess
+ 0
+ rwx
+
+
+ MPUMaster0URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster0URAccess
+ 1
+ denied
+
+
+ MPUMaster0UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster0UWAccess
+ 1
+ denied
+
+
+ MPUMaster0UXAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster0UXAccess
+ 1
+ denied
+
+
+ MPUMaster1Grp15
+ false
+ false
+ false
+
+
+ MPUMaster1SAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster1SAccess
+ 0
+ rwx
+
+
+ MPUMaster1URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster1URAccess
+ 1
+ denied
+
+
+ MPUMaster1UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster1UWAccess
+ 1
+ denied
+
+
+ MPUMaster1UXAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster1UXAccess
+ 1
+ denied
+
+
+ MPUMaster2Grp15
+ false
+ false
+ false
+
+
+ MPUMaster2SAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster2SAccess
+ 0
+ rwx
+
+
+ MPUMaster2URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster2URAccess
+ 1
+ denied
+
+
+ MPUMaster2UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster2UWAccess
+ 1
+ denied
+
+
+ MPUMaster2UXAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster2UXAccess
+ 1
+ denied
+
+
+ MPUMaster3Grp15
+ false
+ false
+ false
+
+
+ MPUMaster3SAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster3SAccess
+ 0
+ rwx
+
+
+ MPUMaster3URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster3URAccess
+ 1
+ denied
+
+
+ MPUMaster3UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster3UWAccess
+ 1
+ denied
+
+
+ MPUMaster3UXAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster3UXAccess
+ 1
+ denied
+
+
+ MPUMaster4Grp15
+ false
+ false
+ false
+
+
+ MPUMaster4URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster4URAccess
+ 1
+ denied
+
+
+ MPUMaster4UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster4UWAccess
+ 1
+ denied
+
+
+ MPUMaster5Grp15
+ false
+ false
+ false
+
+
+ MPUMaster5URAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster5URAccess
+ 1
+ denied
+
+
+ MPUMaster5UWAccess15
+ false
+ false
+ false
+ typeKinetisMPUMaster5UWAccess
+ 1
+ denied
+
+
+ MPUInternalUsageGrp
+ false
+ false
+ true
+
+
+ MPUIsInitialized
+ false
+ 0
+ true
+
+
+ ShrdAXBSGrp
+ 1
+
+
+ AXBSGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceAXBS
+ false
+ false
+
+ false
+
+
+ AXBSBusSlave0_Flash_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave0_Flash_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave0_Flash_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave0_Flash_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave0_Flash_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave0_Flash_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave0_Flash_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave0_Flash_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave0_Flash_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave0_Flash_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave0_Flash_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave0_Flash_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave0_Flash_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave0_Flash_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_HLP
+ 0
+ high
+
+
+ AXBSBusSlave1_SRAM_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave1_SRAM_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave1_SRAM_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave1_SRAM_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave1_SRAM_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave1_SRAM_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave1_SRAM_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave1_SRAM_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave1_SRAM_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave1_SRAM_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave1_SRAM_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave1_SRAM_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave1_SRAM_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave1_SRAM_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_HLP
+ 0
+ high
+
+
+ AXBSBusSlave2_PBRIDGE0_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave2_PBRIDGE0_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave2_PBRIDGE0_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave2_PBRIDGE0_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave2_PBRIDGE0_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave2_PBRIDGE0_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave2_PBRIDGE0_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave2_PBRIDGE0_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave2_PBRIDGE0_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave2_PBRIDGE0_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave2_PBRIDGE0_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave2_PBRIDGE0_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave2_PBRIDGE0_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave2_PBRIDGE0_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_HLP
+ 0
+ high
+
+
+ AXBSBusSlave3_PBRIDGE1_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave3_PBRIDGE1_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave3_PBRIDGE1_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave3_PBRIDGE1_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave3_PBRIDGE1_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave3_PBRIDGE1_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave3_PBRIDGE1_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave3_PBRIDGE1_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave3_PBRIDGE1_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave3_PBRIDGE1_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave3_PBRIDGE1_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave3_PBRIDGE1_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave3_PBRIDGE1_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave3_PBRIDGE1_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_HLP
+ 0
+ high
+
+
+ AXBSBusSlave4_FLEXBUS_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave4_FLEXBUS_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave4_FLEXBUS_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave4_FLEXBUS_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave4_FLEXBUS_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave4_FLEXBUS_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave4_FLEXBUS_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave4_FLEXBUS_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave4_FLEXBUS_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave4_FLEXBUS_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave4_FLEXBUS_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave4_FLEXBUS_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave4_FLEXBUS_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave4_FLEXBUS_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_HLP
+ 0
+ high
+
+
+ AXBSBusSlave5_DDR0_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave5_DDR0_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave5_DDR0_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave5_DDR0_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave5_DDR0_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave5_DDR0_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave5_DDR0_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave5_DDR0_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave5_DDR0_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave5_DDR0_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave5_DDR0_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave5_DDR0_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave5_DDR0_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave5_DDR0_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_HLP
+ 0
+ high
+
+
+ AXBSBusSlave6_DDR1_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave6_DDR1_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave6_DDR1_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave6_DDR1_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave6_DDR1_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave6_DDR1_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave6_DDR1_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave6_DDR1_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave6_DDR1_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave6_DDR1_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave6_DDR1_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave6_DDR1_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave6_DDR1_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave6_DDR1_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_HLP
+ 0
+ high
+
+
+ AXBSBusSlave7_DDR2_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave7_DDR2_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave7_DDR2_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave7_DDR2_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave7_DDR2_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave7_DDR2_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave7_DDR2_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave7_DDR2_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave7_DDR2_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave7_DDR2_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave7_DDR2_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave7_DDR2_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave7_DDR2_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave7_DDR2_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_HLP
+ 0
+ high
+
+
+ AXBSMastersArbitr_Grp
+ false
+ false
+ false
+
+
+ AXBSBusMasterSettingsGrp0
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB0
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp1
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB1
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp2
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB2
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp3
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB3
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp4
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB4
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp5
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB5
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp6
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB6
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp7
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB7
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSInternalUsageGrp
+ false
+ false
+ true
+
+
+ AXBSIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdAIPS0Grp
+ 1
+
+
+ AIPS0Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceAIPS0
+ false
+ false
+
+ false
+
+
+ AIPS0BusMasterGrp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_CODE_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_CODE_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_CODE_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_CODE_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_SYSTEM_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_DMA_EzPort_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS0_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_LCDC_BUS0_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS0_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS0_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS1_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_LCDC_BUS1_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS1_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS0BusMaster_LCDC_BUS1_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS0BusMaster_USBHS_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_USBHS_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS0BusMaster_USBHS_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS0BusMaster_USBHS_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS0BusMaster_ENET_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_ENET_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS0BusMaster_ENET_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS0BusMaster_ENET_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS0PeripheralAccessControlGrp
+ false
+ false
+ false
+
+
+ AIPS0PrphAccessGrp_AIPS0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_AIPS0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_AIPS0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_AIPS0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_AXBS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_AXBS_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_AXBS_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_AXBS_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_DMA
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_DMA_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_DMA_DESCRIPTORS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_FB
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FB_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FB_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FB_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_MPU
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_MPU_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MPU_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MPU_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_FMC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FMC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FMC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FMC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_FTFE
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FTFE_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTFE_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTFE_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_DMA_MULTIPLEXOR0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_DMA_MULTIPLEXOR1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CAN0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CAN0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CAN0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CAN0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SPI0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SPI0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SPI0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SPI0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SPI1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SPI1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SPI1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SPI1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2S0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2S0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2S0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2S0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2S1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2S1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2S1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2S1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CRC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CRC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CRC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CRC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_USBHS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_USBHS_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USBHS_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USBHS_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_USBDCD
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_USBDCD_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USBDCD_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USBDCD_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PDB0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PDB0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PDB0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PDB0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PIT
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PIT_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PIT_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PIT_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_FTM0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FTM0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTM0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTM0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_FTM1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FTM1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTM1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_FTM1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_ADC0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_ADC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_ADC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_ADC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_ADC2
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_ADC2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_ADC2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_ADC2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_RTC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_RTC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RTC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RTC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_VBAT_REGS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_VBAT_REGS_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VBAT_REGS_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VBAT_REGS_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_LPTMR0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_LPTMR0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LPTMR0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LPTMR0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SYSTEM_REGS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SYSTEM_REGS_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SYSTEM_REGS_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SYSTEM_REGS_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_TSI0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_TSI0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_TSI0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_TSI0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SIM_LP
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SIM_LP_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SIM_LP_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SIM_LP_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SIM
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SIM_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SIM_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SIM_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTA
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTA_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTA_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTA_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTB
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTB_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTB_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTB_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTD
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTD_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTD_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTD_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTE
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTE_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTE_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTE_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTF
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTF_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTF_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTF_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_WDOG
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_WDOG_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_WDOG_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_WDOG_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_EWM
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_EWM_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_EWM_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_EWM_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CMT
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CMT_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMT_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMT_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_MCG
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_MCG_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MCG_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MCG_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_OSC0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_OSC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_OSC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_OSC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2C0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2C0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2C1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2C1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART2
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART3
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_USB0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_USB0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USB0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USB0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CMP
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CMP_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMP_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMP_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_VREF
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_VREF_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VREF_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VREF_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_LLWU
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_LLWU_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LLWU_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LLWU_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PMC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PMC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PMC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PMC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SMC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SMC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SMC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SMC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_RCM
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_RCM_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RCM_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RCM_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0InternalUsageGrp
+ false
+ false
+ true
+
+
+ AIPS0IsInitialized
+ false
+ 1
+ false
+
+
+ ShrdAIPS1Grp
+ 1
+
+
+ AIPS1Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceAIPS1
+ false
+ false
+
+ false
+
+
+ AIPS1BusMasterGrp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_CODE_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_CODE_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_CODE_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_CODE_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_SYSTEM_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_DMA_EzPort_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_LCDC_BUS0_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_LCDC_BUS1_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_USBHS_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_ENET_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1PeripheralAccessControlGrp
+ false
+ false
+ false
+
+
+ AIPS1PrphAccessGrp_AIPS1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_AIPS1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_AIPS1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_AIPS1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_RNGA
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_RNGA_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_RNGA_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_RNGA_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_CAN1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_CAN1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_CAN1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_CAN1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC0
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_SPI2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_SPI2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SPI2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SPI2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DDR
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DDR_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DDR_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DDR_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_SDHC
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_SDHC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SDHC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SDHC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_LCDC
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_LCDC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_LCDC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_LCDC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_FTM2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_FTM2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_FTM3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_FTM3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ADC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ADC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ADC3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ADC3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ENET
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ENET_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ENET_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ENET_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DAC0
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DAC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DAC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DAC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_OSC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_OSC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_OSC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_OSC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_UART4
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_UART4_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART4_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART4_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_UART5
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_UART5_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART5_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART5_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1InternalUsageGrp
+ false
+ false
+ true
+
+
+ AIPS1IsInitialized
+ false
+ 1
+ false
+
+
+ ShrdMCMGrp
+ 1
+
+
+ MCMGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceMCM
+ false
+ false
+
+ false
+
+
+ MCMSRAMGrp
+ false
+ false
+ false
+
+
+ MCMSRAML_Grp
+ false
+ false
+ false
+
+
+ MCMWriteProtect0
+ false
+ false
+ false
+ typeKinetisMCMWriteProtect
+ 0
+ disabled
+
+
+ MCMArbitPriority0
+ false
+ false
+ false
+ typeKinetisMCMArbitPriority
+ 0
+ roundRobin
+
+
+ MCMSRAMU_Grp
+ false
+ false
+ false
+
+
+ MCMWriteProtect1
+ false
+ false
+ false
+ typeKinetisMCMWriteProtect
+ 0
+ disabled
+
+
+ MCMArbitPriority1
+ false
+ false
+ false
+ typeKinetisMCMArbitPriority
+ 0
+ roundRobin
+
+
+ MCMETBGrp
+ false
+ false
+ false
+
+
+ MCMETB_ITM2TPIU
+ false
+ false
+ false
+ typeKinetisMCMETB_ITM2TPIU
+ 0
+ enabled
+
+
+ MCMETB_ETM2TPIU
+ false
+ false
+ false
+ typeKinetisMCMETB_ETM2TPIU
+ 0
+ enabled
+
+
+ MCMETB_ResponseType
+ false
+ false
+ false
+ typeKinetisMCMETB_ResponseType
+ 0
+ noResponse
+
+
+ MCMETB_CntRL
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ MCMETB_CntEnable
+ false
+ false
+ false
+ typeKinetisMCMETB_CntEnable
+ 1
+ disabled
+
+
+ MCMInternalUsageGrp
+ false
+ false
+ true
+
+
+ MCMIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdSCBGrp
+ 1
+
+
+ SystemControlGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceSystemControl
+ false
+ false
+
+ false
+
+
+ SystemControlSCBSettingGrp
+ false
+ false
+ false
+
+
+ SystemControlITFolding
+ false
+ false
+ false
+ typeKinetisSystemControlITFolding
+ 0
+ enabled
+
+
+ SystemControlWriteBuffer
+ false
+ false
+ false
+ typeKinetisSystemControlWriteBuffer
+ 0
+ enabled
+
+
+ SystemControlMultiCycleInstruction
+ false
+ false
+ false
+ typeKinetisSystemControlMultiCycleInstruction
+ 0
+ enabled
+
+
+ SystemControlPriorityGrouping
+ false
+ false
+ false
+ typeKinetisSystemControlPriorityGrouping
+ 4
+ 16
+
+
+ SystemControlStackAlignment
+ false
+ false
+ false
+ typeKinetisSystemControlStackAlignment
+ 0
+ 4_byte
+
+
+ SystemControlIgnoreDbusFault
+ false
+ false
+ false
+ typeKinetisSystemControlIgnoreDbusFault
+ 1
+ disabled
+
+
+ SystemControlUsageFaultGrp
+ false
+ false
+ false
+
+
+ SystemControlDivideBy0ZeroTrap
+ false
+ false
+ false
+ typeKinetisSystemControlDivideBy0ZeroTrap
+ 1
+ disabled
+
+
+ SystemControlUnalignedAccessTrap
+ false
+ false
+ false
+ typeKinetisSystemControlUnalignedAccessTrap
+ 1
+ disabled
+
+
+ SystemControlSTIRUnpriviledgedAccess
+ false
+ false
+ false
+ typeKinetisSystemControlSTIRUnpriviledgedAccess
+ 1
+ disabled
+
+
+ SystemControlInternalUsageGrp
+ false
+ false
+ true
+
+
+ SystemControlIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdPMCGrp
+ 1
+
+
+ PMCGrp
+ false
+ false
+ false
+
+
+ PeriphDevicePMC
+ false
+ false
+ PMC
+ false
+
+
+ PMCLVDreset
+ false
+ false
+ false
+ typeKinetisPMCLVDreset
+ 1
+ enabled
+
+
+ PMCLVDvoltageSelect
+ false
+ false
+ false
+ typeKinetisPMCLVDvoltageSelect
+ 0
+ low
+
+
+ PMCLVWvoltageSelect
+ false
+ false
+ false
+ typeKinetisPMCLVWvoltageSelect
+ 0
+ low
+
+
+ PMCBangapBuffer
+ false
+ false
+ false
+ typeKinetisPMCBangapBuffer
+ 0
+ disabled
+
+
+ PMCPMCIntGrp
+ false
+ false
+ true
+
+
+ PMCLVDIntName
+ INT_LVD_LVW
+
+
+ PMCLVDIntNameRequestFeatureGroup
+ false
+ false
+
+
+ PMCLVDIntNameRequest
+ false
+ false
+ false
+ typeKinetisPMCLVDIntNameRequest
+ 1
+ disabled
+
+
+ PMCLVDIntNamePriorityFeatureGroup
+ false
+ false
+
+
+ PMCLVDIntNamePriority
+ false
+ false
+ false
+ typeKinetisPMCLVDIntNamePriority
+ 0
+ 0
+
+
+ DevInit_PMCISRnameLVDGrp
+ false
+ false
+
+
+ PMCISRnameLVD
+ false
+ false
+
+ true
+
+
+ PMCLVDinterrupt
+ false
+ false
+ false
+ typeKinetisPMCLVDinterrupt
+ 1
+ disabled
+
+
+ PMCLVWinterrupt
+ false
+ false
+ false
+ typeKinetisPMCLVWinterrupt
+ 1
+ disabled
+
+
+ PMCInternalUsageGrp
+ false
+ false
+ true
+
+
+ PMCIsInitialized
+ false
+ 0
+ true
+
+
+ ShrdSCBGrp1
+ 1
+
+
+ SIMGrp
+ false
+ false
+ false
+
+
+ PeriphDeviceSIM
+ false
+ false
+ SIM
+ false
+
+
+ SIMCLKOUTGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SIMCLKOUTPin
+ false
+ false
+
+ false
+
+
+ SIMCLKOUTPinSignal
+ false
+ false
+
+
+
+ SIMCLKOUT
+ false
+ false
+ false
+ typeKinetisSIMCLKOUT
+ 0
+ flexbusClk
+
+
+ SIMCMTUARTPAD
+ false
+ false
+ false
+ typeKinetisSIMCMTUARTPAD
+ 0
+ singlePad
+
+
+ SIMSCGCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SIMClkGateOSC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART4
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART5
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateENET
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDAC0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDAC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateRNGA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCAN1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateNFC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDDR
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2S1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSDHC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateLCDC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateEWM
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCMT
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2C0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2C1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSB0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCMP
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateVREF
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateLLWU
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateLPTMR0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSYSTEM_REGS
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateTSI0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTB
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTD
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTE
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTF
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDMA_MULTIPLEXOR0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDMA_MULTIPLEXOR1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCAN0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2S0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCRC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSBHS
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSBDCD
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePDB0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePIT
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateRTC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFB
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateDMA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateMPU
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMInternalUsageGrp
+ false
+ false
+ true
+
+
+ SIMIsInitialized
+ false
+ 0
+ true
+
+
+ Shared_CPUInterrupts
+ 1
+
+
+ CPUInterrupts
+ false
+ false
+ false
+
+
+ IntNMIGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ IntNMI
+ INT_NMI
+
+
+ DevInit_NMINMIInterruptISRNameGrp
+ false
+ false
+
+
+ ISRnameNMI
+ false
+ false
+
+ true
+
+
+ DevInit_Default_ISRGrp
+ false
+ false
+
+
+ DefaultISRGrp
+ false
+ false
+ true
+ false
+
+
+ IntEmpty
+
+ true
+
+
+ ISRDefaultName
+ false
+ false
+ isr_default
+ true
+
+
+ MCU_Reset_Vector_Grp
+ false
+ false
+
+
+ resetVector
+ false
+ false
+ true
+ false
+
+
+ IntVreset
+ INT_Initial_Program_Counter
+ true
+
+
+ ISRnameINITPC
+ false
+ false
+ _startup
+ true
+
+
+ IntHardFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntHardFault
+ INT_Hard_Fault
+
+
+ DevInit_InthardFaultGrp
+ false
+ false
+
+
+ ISRnameHardfault
+ false
+ false
+
+ true
+
+
+ IntMPUGrp
+ false
+ false
+ false
+
+
+ IntMPU
+ INT_UNIMPLEMENTED_A_LINE
+
+
+ DevInit_MPUGrp
+ false
+ false
+
+
+ ISRnameMPU
+ false
+ false
+
+ true
+
+
+ IntBusFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntBusFault
+ INT_Bus_Fault
+
+
+ IntBusFaultPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntBusFaultGrp
+ false
+ false
+
+
+ ISRnameBusFault
+ false
+ false
+
+ true
+
+
+ IntUsageFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntUsageFault
+ INT_Usage_Fault
+
+
+ IntUsageFaultPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntUsageFaultGrp
+ false
+ false
+
+
+ ISRnameUsageFault
+ false
+ false
+
+ true
+
+
+ IntSVCallGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntSVCall
+ INT_SVCall
+
+
+ IntSVCallPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntSVCallGrp
+ false
+ false
+
+
+ ISRnameSVCall
+ false
+ false
+
+ true
+
+
+ IntPendSVGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntPendSV
+ INT_PendableSrvReq
+
+
+ IntPendSVPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntPendSVGrp
+ false
+ false
+
+
+ ISRnamePendSV
+ false
+ false
+
+ true
+
+
+ IntLossOfLockNotFeatureGrp
+ false
+ false
+
+
+ IntLossOfLockGrp
+ false
+ false
+ false
+
+
+ IntLossOfLock
+ INT_MCG
+
+
+ IntLossOfLockPrior
+ false
+ false
+ false
+ medium priority
+
+
+ MCU_Reset_Vector_Grp2
+ false
+ false
+
+
+ ISRnameLossOfLock
+ false
+ false
+
+ true
+
+
+ DDRCondGrp
+ false
+ false
+
+
+ ShrdSCBGrp2
+ 1
+
+
+ DDRGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceDDR
+ false
+ false
+
+ false
+
+
+ DDRClockGateFeatureGroup
+ false
+ false
+
+
+ DDRClockGate
+ false
+ false
+ false
+ true
+ typeKinetisDDRClockGate
+ 0
+ noInit
+
+
+ DDRBusClock
+
+
+
+ DDRLogicPHYClock
+
+
+
+ DDRDRAMClass
+ false
+ false
+ false
+ typeKinetisDDRDRAMClass
+ 0
+ DDR1
+
+
+ DDRDDRAddressSizeTranslation
+ false
+ false
+ false
+ typeKinetisDDRDDRAddressSizeTranslation
+ 0
+ DDRAddressTranslationIsDisabled
+
+
+ DDRDRAMInitGroup
+ false
+ false
+ false
+
+
+ DDRClockPulseWidth
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRegisteredDIMM
+ false
+ false
+ false
+ typeKinetisDDRRegisteredDIMM
+ 0
+ Disabled
+
+
+ DDRDelayLockedLoop
+ false
+ false
+ true
+
+
+ DDRTimeDLL
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDLLResetDelay
+ false
+ false
+ false
+ 1024
+ DEC
+
+
+ DDRDLLResetAdjustDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRNoCommand
+ false
+ false
+ false
+ typeKinetisDDRNoCommand
+ 0
+ Enabled
+
+
+ DDRResynchronizeAfterRefresh
+ false
+ false
+ false
+ typeKinetisDDRResynchronizeAfterRefresh
+ 0
+ Disabled
+
+
+ DDRTimeInitialization
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRInitializationAutoRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRModeRegistersGroup
+ false
+ false
+ true
+
+
+ DDRModeRegisterSetCommandCycleTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeMode
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRModeRegister0
+ false
+ false
+ false
+ 1024
+ HEX
+
+
+ DDRModeRegister1
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ DDRModeRegister2
+ false
+ false
+ false
+ 1024
+ HEX
+
+
+ DDRModeRegister3
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ DDROffChipDriverImpedanceAdjustmentGroup
+ false
+ false
+ true
+
+
+ DDROCDPullDownAdjustmentChipSelect
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDROCDPullUpAdjustmentChipSelect
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDROnDieTerminationGroup
+ false
+ false
+ true
+
+
+ DDRODTReadMapCS
+ false
+ false
+ false
+ typeKinetisDDRODTReadMapCS
+ 0
+ Yes
+
+
+ DDRODTWriteMapCS
+ false
+ false
+ false
+ typeKinetisDDRODTWriteMapCS
+ 0
+ Yes
+
+
+ DDRCommandsGroup
+ false
+ false
+ true
+
+
+ DDRActivateGroup
+ false
+ false
+ true
+
+
+ DDRTimeRASLockout
+ false
+ false
+ false
+ typeKinetisDDRTimeRASLockout
+ 0
+ NotSupported
+
+
+ DDRTimeRASMinimum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRowAccessMaximum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRAStoRASDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRAStoCASDelayInterval
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRowCycleTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeFAW
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadAndWriteAccessGroup
+ false
+ false
+ true
+
+
+ DDRTimeCAStoCASDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLatencyLinear
+ false
+ false
+ false
+ typeKinetisDDRLatencyLinear
+ 0
+ Cycle_0
+
+
+ DDRLatencyGate
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatency
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteRecovery
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteToRead
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBurstModeGroup
+ false
+ false
+ true
+
+
+ DDRBurstLength
+ false
+ false
+ false
+ typeKinetisDDRBurstLength
+ 0
+ Reserved
+
+
+ DDRTimeBurstInterruptInterval
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRInterruptWriteBurst
+ false
+ false
+ false
+ typeKinetisDDRInterruptWriteBurst
+ 0
+ Disabled
+
+
+ DDRPrechargeGroup
+ false
+ false
+ true
+
+
+ DDRTimeClockEnableToPrechargeDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBankPrechargeTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTRPAllBank
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeReadToPrecharge
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteRecoveryAndAutoPrecharge
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRAutoPrecharge
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRConcurrentAutoPrechargeEnable
+ false
+ false
+ false
+ typeKinetisDDRConcurrentAutoPrechargeEnable
+ 0
+ Disabled
+
+
+ DDRRefreshGroup
+ false
+ false
+ true
+
+
+ DDRTimeRefreshCommand
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRefreshCommands
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRAutoRefreshMode
+ false
+ false
+ false
+ typeKinetisDDRAutoRefreshMode
+ 0
+ OnBurst
+
+
+ DDRTimeRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerGroup
+ false
+ false
+ true
+
+
+ DDRAutomaticEntryGroup
+ false
+ false
+ true
+
+
+ DDRLowPowerAutoMode1
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode1
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode2
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode2
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode3
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode3
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode4
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode4
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode5
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode5
+ 0
+ Disabled
+
+
+ DDRLowPowerPowerDownCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerExternalCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerIntervalCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshEnable
+ false
+ false
+ false
+ typeKinetisDDRLowPowerRefreshEnable
+ 0
+ Enabled
+
+
+ DDRSelfRefreshModesGroup
+ false
+ false
+ true
+
+
+ DDRTimeClockLowSelfRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRClockSelfRefreshEntry
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRClockSelfRefreshExit
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTXSNRParameter
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshHold
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRAddressingGroup
+ false
+ false
+ false
+
+
+ DDRChipSelectMap
+ false
+ false
+ false
+ typeKinetisDDRChipSelectMap
+ 0
+ Disabled
+
+
+ DDREightBankMode
+ false
+ false
+ false
+ typeKinetisDDREightBankMode
+ 0
+ Banks4
+
+
+ DDRAddressPins
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRColumnSize
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDatapathWidth
+ false
+ false
+ false
+ typeKinetisDDRDatapathWidth
+ 0
+ Width16bit
+
+
+ DDRAutoPrechargeBit
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBigEndianEnable
+ false
+ false
+ false
+ typeKinetisDDRBigEndianEnable
+ 0
+ LittleEndian
+
+
+ DDRCommandQueueGroup
+ false
+ false
+ false
+
+
+ DDRQueueFullness
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPlacementEnable
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRAddressCollisionEnable
+ false
+ false
+ false
+ typeKinetisDDRAddressCollisionEnable
+ 0
+ Disabled
+
+
+ DDRBankSplitEnable
+ false
+ false
+ false
+ typeKinetisDDRBankSplitEnable
+ 0
+ Disabled
+
+
+ DDRPriorityEnable
+ false
+ false
+ false
+ typeKinetisDDRPriorityEnable
+ 0
+ Disabled
+
+
+ DDRReadWriteSameEnable
+ false
+ false
+ false
+ typeKinetisDDRReadWriteSameEnable
+ 0
+ Disabled
+
+
+ DDRSwapEnable
+ false
+ false
+ false
+ typeKinetisDDRSwapEnable
+ 0
+ Disabled
+
+
+ DDRAgeCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRCommandAgeCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPortsGroup
+ false
+ false
+ true
+
+
+ DDRWRRLatency
+ false
+ false
+ false
+ typeKinetisDDRWRRLatency
+ 0
+ FreeRunning
+
+
+ DDRWRRSharedArbitration
+ false
+ false
+ false
+ typeKinetisDDRWRRSharedArbitration
+ 0
+ Independent
+
+
+ DDRPort0Group
+ false
+ false
+ false
+
+
+ DDRPort0Order
+ false
+ false
+ false
+ typeKinetisDDRPort0Order
+ 0
+ Highest
+
+
+ DDRPort0Type
+ false
+ false
+ false
+ typeKinetisDDRPort0Type
+ 0
+ Asynchronous
+
+
+ DDRPort0ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort0ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort0WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort0WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort0PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort0Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority3Commands
+ 0
+ Lowest
+
+
+ DDRPort1Group
+ false
+ false
+ false
+
+
+ DDRPort1Order
+ false
+ false
+ false
+ typeKinetisDDRPort1Order
+ 0
+ Highest
+
+
+ DDRPort1Type
+ false
+ false
+ false
+ typeKinetisDDRPort1Type
+ 0
+ Asynchronous
+
+
+ DDRPort1ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort1ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort1WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort1WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort1PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort1Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority3Commands
+ 0
+ Lowest
+
+
+ DDRPort2Group
+ false
+ false
+ false
+
+
+ DDRPort2Order
+ false
+ false
+ false
+ typeKinetisDDRPort2Order
+ 0
+ Highest
+
+
+ DDRPort2Type
+ false
+ false
+ false
+ typeKinetisDDRPort2Type
+ 0
+ Asynchronous
+
+
+ DDRPort2ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort2ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort2WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort2WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort2PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort2Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority3Commands
+ 0
+ Lowest
+
+
+ DDRFastWrite
+ false
+ false
+ false
+ typeKinetisDDRFastWrite
+ 0
+ Disabled
+
+
+ DDRAdditionalDelaysGroup
+ false
+ false
+ true
+
+
+ DDRR2RSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRR2WSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRW2RSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRW2WSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYGroup
+ false
+ false
+ false
+
+
+ DDRCommandDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRCommandLatencyReductionEnable
+ false
+ false
+ false
+ typeKinetisDDRCommandLatencyReductionEnable
+ 0
+ Disabled
+
+
+ DDRWriteGroup
+ false
+ false
+ true
+
+
+ DDRPHYWriteLatencyBase
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatencyAdjust
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatencyReductionEnable
+ false
+ false
+ false
+ typeKinetisDDRWriteLatencyReductionEnable
+ 0
+ Disabled
+
+
+ DDRReadGroup
+ false
+ false
+ true
+
+
+ DDRPHYReadLatency
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadLatencyAdjust
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadDataEnableBase
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRUpdateGroup
+ false
+ false
+ true
+
+
+ DDRDFICTRLUPDMinimum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType0
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType1
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType2
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType3
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTDFIPHYUPDRESPParameter
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDRAMClockGroup
+ false
+ false
+ true
+
+
+ DDRDFIClockDisableDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIClockEnableDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRODTAlternateEnable
+ false
+ false
+ false
+ typeKinetisDDRODTAlternateEnable
+ 0
+ Disabled
+
+
+ DDRPinsGroup
+ false
+ false
+ false
+
+
+ DDRPinEnableForAllDDRIO
+ false
+ false
+ false
+ typeKinetisDDRPinEnableForAllDDRIO
+ 0
+ disabled
+
+
+ DDRDDRConfigurationSelect
+ false
+ false
+ false
+ typeKinetisDDRDDRConfigurationSelect
+ 0
+ LPDDRHalfStrength
+
+
+ DDRDDRSelfRefreshEnable
+ false
+ false
+ false
+ typeKinetisDDRDDRSelfRefreshEnable
+ 0
+ disabled
+
+
+ DDRSpareDelayCtrl
+ false
+ false
+ false
+ typeKinetisDDRSpareDelayCtrl
+ 0
+ NoBuffer
+
+
+ DDRODTResistor
+ false
+ false
+ false
+ typeKinetisDDRODTResistor
+ 0
+ ODTDisabled
+
+
+ DDRPin0Group
+ false
+ false
+ false
+
+
+ DDRPin0
+ false
+ false
+
+ false
+
+
+ DDRPin0Signal
+ false
+ false
+
+
+
+ DDRPin1Group
+ false
+ false
+ false
+
+
+ DDRPin1
+ false
+ false
+
+ false
+
+
+ DDRPin1Signal
+ false
+ false
+
+
+
+ DDRPin2Group
+ false
+ false
+ false
+
+
+ DDRPin2
+ false
+ false
+
+ false
+
+
+ DDRPin2Signal
+ false
+ false
+
+
+
+ DDRPin3Group
+ false
+ false
+ false
+
+
+ DDRPin3
+ false
+ false
+
+ false
+
+
+ DDRPin3Signal
+ false
+ false
+
+
+
+ DDRPin4Group
+ false
+ false
+ false
+
+
+ DDRPin4
+ false
+ false
+
+ false
+
+
+ DDRPin4Signal
+ false
+ false
+
+
+
+ DDRPin5Group
+ false
+ false
+ false
+
+
+ DDRPin5
+ false
+ false
+
+ false
+
+
+ DDRPin5Signal
+ false
+ false
+
+
+
+ DDRPin6Group
+ false
+ false
+ false
+
+
+ DDRPin6
+ false
+ false
+
+ false
+
+
+ DDRPin6Signal
+ false
+ false
+
+
+
+ DDRPin7Group
+ false
+ false
+ false
+
+
+ DDRPin7
+ false
+ false
+
+ false
+
+
+ DDRPin7Signal
+ false
+ false
+
+
+
+ DDRPin8Group
+ false
+ false
+ false
+
+
+ DDRPin8
+ false
+ false
+
+ false
+
+
+ DDRPin8Signal
+ false
+ false
+
+
+
+ DDRPin9Group
+ false
+ false
+ false
+
+
+ DDRPin9
+ false
+ false
+
+ false
+
+
+ DDRPin9Signal
+ false
+ false
+
+
+
+ DDRPin10Group
+ false
+ false
+ false
+
+
+ DDRPin10
+ false
+ false
+
+ false
+
+
+ DDRPin10Signal
+ false
+ false
+
+
+
+ DDRPin11Group
+ false
+ false
+ false
+
+
+ DDRPin11
+ false
+ false
+
+ false
+
+
+ DDRPin11Signal
+ false
+ false
+
+
+
+ DDRPin12Group
+ false
+ false
+ false
+
+
+ DDRPin12
+ false
+ false
+
+ false
+
+
+ DDRPin12Signal
+ false
+ false
+
+
+
+ DDRPin13Group
+ false
+ false
+ false
+
+
+ DDRPin13
+ false
+ false
+
+ false
+
+
+ DDRPin13Signal
+ false
+ false
+
+
+
+ DDRPin14Group
+ false
+ false
+ false
+
+
+ DDRPin14
+ false
+ false
+
+ false
+
+
+ DDRPin14Signal
+ false
+ false
+
+
+
+ DDRPin15Group
+ false
+ false
+ false
+
+
+ DDRPin15
+ false
+ false
+
+ false
+
+
+ DDRPin15Signal
+ false
+ false
+
+
+
+ DDRPin16Group
+ false
+ false
+ false
+
+
+ DDRPin16
+ false
+ false
+
+ false
+
+
+ DDRPin16Signal
+ false
+ false
+
+
+
+ DDRPin17Group
+ false
+ false
+ false
+
+
+ DDRPin17
+ false
+ false
+
+ false
+
+
+ DDRPin17Signal
+ false
+ false
+
+
+
+ DDRPin19Group
+ false
+ false
+ false
+
+
+ DDRPin19
+ false
+ false
+
+ false
+
+
+ DDRPin19Signal
+ false
+ false
+
+
+
+ DDRPin20Group
+ false
+ false
+ false
+
+
+ DDRPin20
+ false
+ false
+
+ false
+
+
+ DDRPin20Signal
+ false
+ false
+
+
+
+ DDRPin21Group
+ false
+ false
+ false
+
+
+ DDRPin21
+ false
+ false
+
+ false
+
+
+ DDRPin21Signal
+ false
+ false
+
+
+
+ DDRPin23Group
+ false
+ false
+ false
+
+
+ DDRPin23
+ false
+ false
+
+ false
+
+
+ DDRPin23Signal
+ false
+ false
+
+
+
+ DDRPin24Group
+ false
+ false
+ false
+
+
+ DDRPin24
+ false
+ false
+
+ false
+
+
+ DDRPin24Signal
+ false
+ false
+
+
+
+ DDRPin25Group
+ false
+ false
+ false
+
+
+ DDRPin25
+ false
+ false
+
+ false
+
+
+ DDRPin25Signal
+ false
+ false
+
+
+
+ DDRPin26Group
+ false
+ false
+ false
+
+
+ DDRPin26
+ false
+ false
+
+ false
+
+
+ DDRPin26Signal
+ false
+ false
+
+
+
+ DDRPin27Group
+ false
+ false
+ false
+
+
+ DDRPin27
+ false
+ false
+
+ false
+
+
+ DDRPin27Signal
+ false
+ false
+
+
+
+ DDRPin28Group
+ false
+ false
+ false
+
+
+ DDRPin28
+ false
+ false
+
+ false
+
+
+ DDRPin28Signal
+ false
+ false
+
+
+
+ DDRPin29Group
+ false
+ false
+ false
+
+
+ DDRPin29
+ false
+ false
+
+ false
+
+
+ DDRPin29Signal
+ false
+ false
+
+
+
+ DDRPin30Group
+ false
+ false
+ false
+
+
+ DDRPin30
+ false
+ false
+
+ false
+
+
+ DDRPin30Signal
+ false
+ false
+
+
+
+ DDRPin31Group
+ false
+ false
+ false
+
+
+ DDRPin31
+ false
+ false
+
+ false
+
+
+ DDRPin31Signal
+ false
+ false
+
+
+
+ DDRPin32Group
+ false
+ false
+ false
+
+
+ DDRPin32
+ false
+ false
+
+ false
+
+
+ DDRPin32Signal
+ false
+ false
+
+
+
+ DDRPin33Group
+ false
+ false
+ false
+
+
+ DDRPin33
+ false
+ false
+
+ false
+
+
+ DDRPin33Signal
+ false
+ false
+
+
+
+ DDRPin34Group
+ false
+ false
+ false
+
+
+ DDRPin34
+ false
+ false
+
+ false
+
+
+ DDRPin34Signal
+ false
+ false
+
+
+
+ DDRPin35Group
+ false
+ false
+ false
+
+
+ DDRPin35
+ false
+ false
+
+ false
+
+
+ DDRPin35Signal
+ false
+ false
+
+
+
+ DDRPin36Group
+ false
+ false
+ false
+
+
+ DDRPin36
+ false
+ false
+
+ false
+
+
+ DDRPin36Signal
+ false
+ false
+
+
+
+ DDRPin37Group
+ false
+ false
+ false
+
+
+ DDRPin37
+ false
+ false
+
+ false
+
+
+ DDRPin37Signal
+ false
+ false
+
+
+
+ DDRPin38Group
+ false
+ false
+ false
+
+
+ DDRPin38
+ false
+ false
+
+ false
+
+
+ DDRPin38Signal
+ false
+ false
+
+
+
+ DDRPin39Group
+ false
+ false
+ false
+
+
+ DDRPin39
+ false
+ false
+
+ false
+
+
+ DDRPin39Signal
+ false
+ false
+
+
+
+ DDRPin40Group
+ false
+ false
+ false
+
+
+ DDRPin40
+ false
+ false
+
+ false
+
+
+ DDRPin40Signal
+ false
+ false
+
+
+
+ DDRPin41Group
+ false
+ false
+ false
+
+
+ DDRPin41
+ false
+ false
+
+ false
+
+
+ DDRPin41Signal
+ false
+ false
+
+
+
+ DDRPin42Group
+ false
+ false
+ false
+
+
+ DDRPin42
+ false
+ false
+
+ false
+
+
+ DDRPin42Signal
+ false
+ false
+
+
+
+ DDRPin43Group
+ false
+ false
+ false
+
+
+ DDRPin43
+ false
+ false
+
+ false
+
+
+ DDRPin43Signal
+ false
+ false
+
+
+
+ DDRPin46Group
+ false
+ false
+ false
+
+
+ DDRPin46
+ false
+ false
+
+ false
+
+
+ DDRPin46Signal
+ false
+ false
+
+
+
+ DDRPin47Group
+ false
+ false
+ false
+
+
+ DDRPin47
+ false
+ false
+
+ false
+
+
+ DDRPin47Signal
+ false
+ false
+
+
+
+ DDRPin48Group
+ false
+ false
+ false
+
+
+ DDRPin48
+ false
+ false
+
+ false
+
+
+ DDRPin48Signal
+ false
+ false
+
+
+
+ DDRPin49Group
+ false
+ false
+ false
+
+
+ DDRPin49
+ false
+ false
+
+ false
+
+
+ DDRPin49Signal
+ false
+ false
+
+
+
+ DDRPin50Group
+ false
+ false
+ false
+
+
+ DDRPin50
+ false
+ false
+
+ false
+
+
+ DDRPin50Signal
+ false
+ false
+
+
+
+ DDRPin51Group
+ false
+ false
+ false
+
+
+ DDRPin51
+ false
+ false
+
+ false
+
+
+ DDRPin51Signal
+ false
+ false
+
+
+
+ DDRPin52Group
+ false
+ false
+ false
+
+
+ DDRPin52
+ false
+ false
+
+ false
+
+
+ DDRPin52Signal
+ false
+ false
+
+
+
+ DDRPin53Group
+ false
+ false
+ false
+
+
+ DDRPin53
+ false
+ false
+
+ false
+
+
+ DDRPin53Signal
+ false
+ false
+
+
+
+ DDRPin54Group
+ false
+ false
+ false
+
+
+ DDRPin54
+ false
+ false
+
+ false
+
+
+ DDRPin54Signal
+ false
+ false
+
+
+
+ DDRPin55Group
+ false
+ false
+ false
+
+
+ DDRPin55
+ false
+ false
+
+ false
+
+
+ DDRPin55Signal
+ false
+ false
+
+
+
+ DDRPin56Group
+ false
+ false
+ false
+
+
+ DDRPin56
+ false
+ false
+
+ false
+
+
+ DDRPin56Signal
+ false
+ false
+
+
+
+ DDRPin57Group
+ false
+ false
+ false
+
+
+ DDRPin57
+ false
+ false
+
+ false
+
+
+ DDRPin57Signal
+ false
+ false
+
+
+
+ DDRPin58Group
+ false
+ false
+ false
+
+
+ DDRPin58
+ false
+ false
+
+ false
+
+
+ DDRPin58Signal
+ false
+ false
+
+
+
+ DDRPin59Group
+ false
+ false
+ false
+
+
+ DDRPin59
+ false
+ false
+
+ false
+
+
+ DDRPin59Signal
+ false
+ false
+
+
+
+ DDRPin60Group
+ false
+ false
+ false
+
+
+ DDRPin60
+ false
+ false
+
+ false
+
+
+ DDRPin60Signal
+ false
+ false
+
+
+
+ DDRPin61Group
+ false
+ false
+ false
+
+
+ DDRPin61
+ false
+ false
+
+ false
+
+
+ DDRPin61Signal
+ false
+ false
+
+
+
+ DDRPin62Group
+ false
+ false
+ false
+
+
+ DDRPin62
+ false
+ false
+
+ false
+
+
+ DDRPin62Signal
+ false
+ false
+
+
+
+ DDRPin63Group
+ false
+ false
+ false
+
+
+ DDRPin63
+ false
+ false
+
+ false
+
+
+ DDRPin63Signal
+ false
+ false
+
+
+
+ DDRPin64Group
+ false
+ false
+ false
+
+
+ DDRPin64
+ false
+ false
+
+ false
+
+
+ DDRPin64Signal
+ false
+ false
+
+
+
+ DDRPin65Group
+ false
+ false
+ false
+
+
+ DDRPin65
+ false
+ false
+
+ false
+
+
+ DDRPin65Signal
+ false
+ false
+
+
+
+ DDRPin66Group
+ false
+ false
+ false
+
+
+ DDRPin66
+ false
+ false
+
+ false
+
+
+ DDRPin66Signal
+ false
+ false
+
+
+
+ DDRPin73Group
+ false
+ false
+ false
+
+
+ DDRPin73
+ false
+ false
+
+ false
+
+
+ DDRPin73Signal
+ false
+ false
+
+
+
+ DDRPin74Group
+ false
+ false
+ false
+
+
+ DDRPin74
+ false
+ false
+
+ false
+
+
+ DDRPin74Signal
+ false
+ false
+
+
+
+ DDRPin75Group
+ false
+ false
+ false
+
+
+ DDRPin75
+ false
+ false
+
+ false
+
+
+ DDRPin75Signal
+ false
+ false
+
+
+
+ DDRInterruptsGroup
+ false
+ false
+ false
+
+
+ DDRInterrupt
+
+
+
+ DDRInterruptRequestFeatureGroup
+ false
+ false
+
+
+ DDRInterruptRequest
+ false
+ false
+ false
+ true
+ typeKinetisDDRInterruptRequest
+ 1
+ disabled
+
+
+ DDRInterruptPriorityFeatureGroup
+ false
+ false
+
+
+ DDRInterruptPriority
+ false
+ false
+ false
+ true
+ typeKinetisDDRInterruptPriority
+ 0
+ 0
+
+
+ DevInit_DDRISRHandleNameGrp
+ false
+ false
+
+
+ DDRISRHandleName
+ false
+ false
+
+ true
+
+
+ DDRInterruptAnyFlagEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptAnyFlagEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDLLResyncFinishedEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDLLResyncFinishedEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDFICompleteEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDFICompleteEnable
+ 0
+ Disabled
+
+
+ DDRInterruptWriteFinishedEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptWriteFinishedEnable
+ 0
+ Disabled
+
+
+ DDRInterruptODTConfigErrorEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptODTConfigErrorEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDDR2MobileEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDDR2MobileEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDRAMInitCompleteEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDRAMInitCompleteEnable
+ 0
+ Disabled
+
+
+ DDRInterruptMultipleOutOfRangeEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptMultipleOutOfRangeEnable
+ 0
+ Disabled
+
+
+ DDRInterruptSingleOutOfRangeEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptSingleOutOfRangeEnable
+ 0
+ Disabled
+
+
+ DDRInternalUsageGrp
+ false
+ false
+ true
+
+
+ DDRIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdFBusGrp
+ 1
+
+
+ ExternalBusGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceExternalBus
+ false
+ false
+
+ false
+
+
+ ExternalBusFBSecurity
+ false
+ false
+ false
+ typeKinetisExternalBusFBSecurity
+ 0
+ AllDisallowed
+
+
+ ExternalBusChipSelectsGrp
+ false
+ false
+ true
+
+
+ ExternalBusCS0
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS0BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS0BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize0
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced0
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS0WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS0WaitStates
+ false
+ false
+ false
+ 63
+ DEC
+
+
+ ExternalBusCS0SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS0SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS0ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS0AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 3
+ 11
+
+
+ ExternalBusCS0ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 3
+ 11
+
+
+ ExternalBusCS0WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 3
+ 11
+
+
+ ExternalBusCS0BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS0AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS0PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS0ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS0BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS0BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS0PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS1
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS1BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS1BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize1
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced1
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS1WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS1WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS1SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS1SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS1ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS1AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS1ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS1WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS1BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS1AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS1PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS1ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS1BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS1BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS1PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS2
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS2BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS2BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize2
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced2
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS2WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS2WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS2SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS2SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS2ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS2AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS2ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS2WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS2BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS2AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS2PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS2ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS2BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS2BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS2PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS3
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS3BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS3BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize3
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced3
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS3WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS3WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS3SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS3SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS3ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS3AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS3ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS3WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS3BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS3AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS3PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS3ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS3BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS3BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS3PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS4
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS4BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS4BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize4
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced4
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS4WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS4WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS4SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS4SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS4ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS4AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS4ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS4WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS4BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS4AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS4PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS4ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS4BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS4BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS4PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS5
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS5BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS5BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize5
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced5
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS5WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS5WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS5SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS5SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS5ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS5AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS5ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS5WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS5BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS5AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS5PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS5ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS5BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS5BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS5PinSignal
+ false
+ false
+
+
+
+ ExternalBusAddrPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusA16PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr16Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr16PinSignal
+ false
+ false
+
+
+
+ ExternalBusA17PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr17PinSignal
+ false
+ false
+
+
+
+ ExternalBusA18PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr18PinSignal
+ false
+ false
+
+
+
+ ExternalBusA19PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr19Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr19PinSignal
+ false
+ false
+
+
+
+ ExternalBusA20PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr20Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr20PinSignal
+ false
+ false
+
+
+
+ ExternalBusA21PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr21Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr21PinSignal
+ false
+ false
+
+
+
+ ExternalBusA22PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr22Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr22PinSignal
+ false
+ false
+
+
+
+ ExternalBusA23PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr23Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr23PinSignal
+ false
+ false
+
+
+
+ ExternalBusA24PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr24Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr24PinSignal
+ false
+ false
+
+
+
+ ExternalBusA25PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr25Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr25PinSignal
+ false
+ false
+
+
+
+ ExternalBusA26PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr26Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr26PinSignal
+ false
+ false
+
+
+
+ ExternalBusA27PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr27Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr27PinSignal
+ false
+ false
+
+
+
+ ExternalBusA28PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr28Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr28PinSignal
+ false
+ false
+
+
+
+ ExternalBusA29PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr29Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr29PinSignal
+ false
+ false
+
+
+
+ ExternalBusDataPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusD0PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData0PinSignal
+ false
+ false
+
+
+
+ ExternalBusD1PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData1PinSignal
+ false
+ false
+
+
+
+ ExternalBusD2PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData2PinSignal
+ false
+ false
+
+
+
+ ExternalBusD3PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData3PinSignal
+ false
+ false
+
+
+
+ ExternalBusD4PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData4PinSignal
+ false
+ false
+
+
+
+ ExternalBusD5PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData5PinSignal
+ false
+ false
+
+
+
+ ExternalBusD6PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData6Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData6PinSignal
+ false
+ false
+
+
+
+ ExternalBusD7PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData7Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData7PinSignal
+ false
+ false
+
+
+
+ ExternalBusD8PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData8Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData8PinSignal
+ false
+ false
+
+
+
+ ExternalBusD9PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData9Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData9PinSignal
+ false
+ false
+
+
+
+ ExternalBusD10PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData10Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData10PinSignal
+ false
+ false
+
+
+
+ ExternalBusD11PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData11Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData11PinSignal
+ false
+ false
+
+
+
+ ExternalBusD12PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData12Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData12PinSignal
+ false
+ false
+
+
+
+ ExternalBusD13PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData13Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData13PinSignal
+ false
+ false
+
+
+
+ ExternalBusD14PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData14Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData14PinSignal
+ false
+ false
+
+
+
+ ExternalBusD15PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData15Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData15PinSignal
+ false
+ false
+
+
+
+ ExternalBusD16PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData16Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData16PinSignal
+ false
+ false
+
+
+
+ ExternalBusD17PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData17PinSignal
+ false
+ false
+
+
+
+ ExternalBusD18PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData18PinSignal
+ false
+ false
+
+
+
+ ExternalBusD19PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData19Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData19PinSignal
+ false
+ false
+
+
+
+ ExternalBusD20PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData20Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData20PinSignal
+ false
+ false
+
+
+
+ ExternalBusD21PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData21Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData21PinSignal
+ false
+ false
+
+
+
+ ExternalBusD22PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData22Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData22PinSignal
+ false
+ false
+
+
+
+ ExternalBusD23PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData23Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData23PinSignal
+ false
+ false
+
+
+
+ ExternalBusD24PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData24Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData24PinSignal
+ false
+ false
+
+
+
+ ExternalBusD25PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData25Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData25PinSignal
+ false
+ false
+
+
+
+ ExternalBusD26PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData26Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData26PinSignal
+ false
+ false
+
+
+
+ ExternalBusD27PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData27Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData27PinSignal
+ false
+ false
+
+
+
+ ExternalBusD28PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData28Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData28PinSignal
+ false
+ false
+
+
+
+ ExternalBusD29PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData29Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData29PinSignal
+ false
+ false
+
+
+
+ ExternalBusD30PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData30Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData30PinSignal
+ false
+ false
+
+
+
+ ExternalBusD31PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData31Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData31PinSignal
+ false
+ false
+
+
+
+ ExternalBusControlPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl0PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl0PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl1PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl1PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl2PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl2PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl3PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl3PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl4PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl4PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl5PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl5PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl6PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl6Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl6PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl7PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl7Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl7PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl13PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl13Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl13PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl14PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl14Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl14PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl17PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl17PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl18PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl18PinSignal
+ false
+ false
+
+
+
+ _ExtMemGrp
+ false
+ 0
+ false
+ true
+
+
+ ExternalBusInternalUsageGrp
+ false
+ false
+ true
+
+
+ ExternalBusIsInitialized
+ false
+ 1
+ false
+
+
+ LowPowerModesGrp
+ false
+ false
+ false
+
+
+ Shared_CPULowPowerGrp
+ 1
+
+
+ AllowedPowerModesGrp
+ false
+ false
+ false
+
+
+ SMC_AHSRUNCondGrp
+ false
+ false
+
+
+ SMC_AHSRUN
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ SMC_AVLP
+ false
+ false
+ false
+ 0
+ true
+
+
+ SMC_ALLS
+ false
+ false
+ false
+ 0
+ true
+
+
+ SMC_AVLLS
+ false
+ false
+ false
+ 0
+ true
+
+
+ ShrdLLWUGrp
+ 1
+
+
+ LLWUGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceLLWU
+ false
+ false
+
+ false
+
+
+ LLWULLWUSettingGrp
+ false
+ false
+ false
+
+
+ LLWUExtPin0
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan0Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin1
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan1Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin2
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan2Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin3
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan3Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin4
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan4Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin5
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan5Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin6
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan6Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin7
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan7Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin8
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan8Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin9
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan9Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin10
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan10Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin11
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan11Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin12
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan12Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin13
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan13Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin14
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan14Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin15
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan15Signal
+ false
+ false
+
+ true
+
+
+ LLWUIntModule0
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule1
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule2
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule3
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule4
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule5
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule7
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUFiltr1
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUFilt1In
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ LLWUFilt1ExtPin0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin0Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin1Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin2Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin3Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin4Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin5Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin6Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin7Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin8Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin9Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin10Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin11Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin12Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin13Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin14Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin15Signal
+ false
+ false
+
+ true
+
+
+ LLWUFiltr2
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUFilt2In
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ LLWUFilt2ExtPin0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin0Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin1Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin2Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin3Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin4Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin5Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin6Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin7Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin8Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin9Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin10Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin11Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin12Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin13Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin14Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin15Signal
+ false
+ false
+
+ true
+
+
+ LLWUReset
+ false
+ false
+ false
+ true
+ true
+
+
+ LLWUResetPinFilter
+ false
+ false
+ false
+ typeKinetisLLWUResetPinFilter
+ 0
+ disabled
+
+
+ LLWUInterruptsGroup
+ false
+ false
+ false
+
+
+ LLWUIntCommon
+
+
+
+ LLWUIntCommonRequestFeatureGroup
+ false
+ false
+
+
+ LLWUIntCommonRequest
+ false
+ false
+ false
+ true
+ typeKinetisLLWUIntCommonRequest
+ 1
+ disabled
+
+
+ LLWUIntCommonPriorityFeatureGroup
+ false
+ false
+
+
+ LLWUIntCommonPriority
+ false
+ false
+ false
+ true
+ typeKinetisLLWUIntCommonPriority
+ 0
+ 0
+
+
+ DevInit_LLWUISRHandleCommonGrp
+ false
+ false
+
+
+ LLWUISRHandleCommon
+ false
+ false
+
+ true
+
+
+ LLWUInternalUsageGrp
+ false
+ false
+ true
+
+
+ LLWUIsInitialized
+ false
+ 1
+ false
+
+
+ Shared_CPULowPowerGrp0
+ 1
+
+
+ SetLowPowerModeGrp
+ false
+ false
+
+
+ SetOperationModeGrp
+ false
+ false
+ false
+
+
+ SetOperationMode_WAIT
+ false
+ false
+ false
+
+
+ SetOperationMode_WAIT_SLEEPONEXIT
+ false
+ false
+ false
+ 1
+ false
+
+
+ SetOperationMode_SLEEP
+ false
+ false
+ false
+
+
+ SetOperationMode_SLEEP_SLEEPONEXIT
+ false
+ false
+ false
+ 1
+ false
+
+
+ SetOperationMode_STOP
+ false
+ false
+ false
+ false
+ false
+
+
+ SetOperationMode_STOP_Sel
+ false
+ false
+ false
+ 0
+ 0
+
+
+ SpeedModeList
+ false
+ 1
+ false
+ true
+
+
+ SpeedMode0
+ false
+ false
+ true
+
+
+ ClkSrcSettingsGrpSpeedMode0
+ false
+ false
+ false
+
+
+ IRC_32kHzSpeedMode0
+ false
+ false
+ false
+ 0.032768
+
+
+ IRC_4MHzSpeedMode0
+ false
+ 2
+
+
+ SYSTEM_OSCSpeedMode0
+ false
+ false
+ false
+ 8
+
+
+ OSC1CLKSpeedMode0
+ false
+ false
+ false
+ 8
+
+
+ RTC_OSCSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ _SYSTEM_PRESCALER0
+ false
+ false
+ false
+
+
+ IRCLKSelSpeedMode0
+ false
+ false
+ false
+ IRC_32kHz
+
+
+ MCG_ERCLKSelSpeedMode0
+ false
+ false
+ false
+ SYSTEM_OSC
+
+
+ PLLREFSEL0SelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ PLLREFSEL1SelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ ERCLK32KSelSpeedMode0
+ false
+ false
+ false
+ SYSTEM_OSC
+
+
+ MCG_FLL_RCLKSelSpeedMode0
+ false
+ false
+ false
+ IRC_32kHz
+
+
+ MCG_FRDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_FLL_MFactorSpeedMode0
+ false
+ false
+ false
+ 640
+
+
+ MCG_PRDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_VDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_PRDIV1SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_VDIV1SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCGPLLCSCLKSelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCGOUTSelSpeedMode0
+ false
+ false
+ false
+ MCGFLLCLK
+
+
+ VLPRSpeedMode0
+ false
+ false
+ false
+ false
+ false
+
+
+ VLPREntrySpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ VLPExitOnIntSpeedMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ CLKModeSpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ MCGModeSelSpeedMode0
+ false
+ 0
+ 0
+
+
+ MCGOutputSpeedMode0
+ false
+ 20.97152
+
+
+ IRCLKClkSpeedMode0
+ 0.032768
+
+
+ ERCLKClkSpeedMode0
+ 0
+
+
+ ERCLK32KClkSpeedMode0
+ 0
+
+
+ FLLFixedClkSpeedMode0
+ 16.384
+
+
+ SystemClocksGrp0
+ false
+ false
+ true
+
+
+ OUTDIV1PrescSpeedMode0
+ false
+ false
+ false
+ 1
+
+
+ OUTDIV1Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ CoreClockSpeedMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ OUTDIV2PrescSpeedMode0
+ false
+ false
+ false
+ 1
+
+
+ OUTDIV2Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ BusClockSpeedMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ OUTDIV3PrescSpeedMode0
+ false
+ false
+ false
+ 2
+
+
+ OUTDIV3Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ ExternalBusClockSpeedMode0
+ false
+ false
+ false
+ 10.48576
+
+
+ OUTDIV4PrescSpeedMode0
+ false
+ false
+ false
+ 2
+
+
+ OUTDIV4Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ FlashClockSpeedMode0
+ false
+ false
+ false
+ 10.48576
+
+
+ USB0_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ USBHS_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ PLLFLLCLkSelSpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ PLLFLLSelSpeedMode0
+ false
+ false
+ false
+ MCGFLLCLK
+
+
+ PLLFLLClockSpeedMode0
+ false
+ 20.97152
+
+
+ I2S0_CLKINCondGrp0
+ false
+ false
+
+
+ I2S0_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ I2S1_CLKINCondGrp0
+ false
+ false
+
+
+ I2S1_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ I2SClockCondGrp0
+ false
+ false
+
+
+ I2SClockGrp0
+ false
+ false
+ true
+
+
+ I2S0_MclkClkSrcCondGrp0
+ false
+ false
+
+
+ I2S0_MclkPinSourceSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ I2S1_MclkClkSrcCondGrp0
+ false
+ false
+
+
+ I2S1_MclkPinSourceSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+
+
+ CPUCond
+ 1
+
+
+ SharedCpuMethodsInvisibleGroup
+ false
+ false
+
+
+ SetClockConfiguration
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SetClockConfiguration
+
+
+ GetClockConfiguration
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ GetClockConfiguration
+
+
+ SetOperationMode
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SetOperationMode
+
+
+ EnableInt
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ EnableInt
+
+
+ DisableInt
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ DisableInt
+
+
+ GetLLSWakeUpFlagsPDD2CondGrp
+ false
+ false
+
+
+ GetLLSWakeUpFlagsCondGrp
+ false
+ false
+
+
+ GetLLSWakeUpFlags
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ GetLLSWakeUpFlags
+
+
+ OpenBackDoor
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ OpenBackDoor
+
+
+ FlexNVMfeatureMethodsGrp
+ false
+ false
+
+
+ GetFlexNVMPartitionCode
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ GetFlexNVMPartitionCode
+
+
+ SetFlexNVMPartition
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ SetFlexNVMPartition
+
+
+ SetFlexRAMFunction
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ SetFlexRAMFunction
+
+
+ MCGAutoTrim
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ MCGAutoTrim
+
+
+ VLPModeEnable
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ VLPModeEnable
+
+
+ VLPModeDisable
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ VLPModeDisable
+
+
+ SystemReset
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SystemReset
+
+
+
+
+ EventModule
+ false
+ false
+ Events
+
+
+ EvntsShrdGrp
+ 1
+
+
+ SharedCommonCpuEventsInvisibleGroup
+ false
+ false
+
+
+ OnReset
+ false
+ false
+ false
+ false
+ false
+ false
+ no
+
+
+ OnResetName
+ false
+ false
+ Cpu_OnReset
+
+
+ OnNMIINT
+ true
+ false
+ false
+ true
+ true
+ true
+ always
+
+
+ OnNMIINTName
+ false
+ false
+ Cpu_OnNMIINT
+
+
+ OnHardFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnHardFaultName
+ false
+ false
+ Cpu_OnHardFault
+
+
+ OnBusFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnBusFaultName
+ false
+ false
+ Cpu_OnBusFault
+
+
+ OnUsageFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnUsageFaultName
+ false
+ false
+ Cpu_OnUsageFault
+
+
+ OnSupervisorCall
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnSupervisorCallName
+ false
+ false
+ Cpu_OnSupervisorCall
+
+
+ OnPendableService
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnPendableServiceName
+ false
+ false
+ Cpu_OnPendableService
+
+
+ CPUCond0
+ false
+ false
+
+
+ OnLossOfLockINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfLockINTName
+ false
+ false
+ Cpu_OnLossOfLockINT
+
+
+ LossOfClockOSC0EvntCondGrp
+ false
+ false
+
+
+ OnLossOfClockOSC0
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockOSC0Name
+ false
+ false
+ Cpu_OnLossOfClockOSC0
+
+
+ LossOfClockRTCEvntCondGrp0
+ false
+ false
+
+
+ OnLossOfClockRTC
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockRTCName
+ false
+ false
+ Cpu_OnLossOfClockRTC
+
+
+ LossOfClockOSC1EvntCondGrp
+ false
+ false
+
+
+ OnLossOfClockOSC1
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockOSC1Name
+ false
+ false
+ Cpu_OnLossOfClockOSC1
+
+
+ OnLowVoltageINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLowVoltageINTName
+ false
+ false
+ Cpu_OnLowVoltageINT
+
+
+ OnLLSWakeUpINTCondGrp
+ false
+ false
+
+
+ OnLLSWakeUpINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLLSWakeUpINTName
+ false
+ false
+ Cpu_OnLLSWakeUpINT
+
+
+ DDREvntCondGrp
+ false
+ false
+
+
+ OnDDRINT
+ true
+ false
+ false
+ false
+ false
+ true
+ never
+
+
+ OnDDRINTName
+ false
+ false
+ Cpu_OnDDRINT
+
+
+
+ L
+
+
+ 0
+ GNU C Compiler
+
+
+ C_CompilerIdentificationLong
+ false
+ GNU C Compiler
+ true
+
+
+ PESLsupport
+ false
+ false
+ true
+ 1
+ false
+
+
+ OSEKsupport
+ false
+ false
+ true
+ 1
+ false
+
+
+ NotRapidGrp
+ false
+ true
+
+
+ UnhandledVectorsBehavior
+ false
+ false
+ true
+ 0
+ true
+
+
+ UnhandledVectorsBehaviorFeatureGrp
+ false
+ true
+
+
+ UnhandledIntCode
+ false
+ (string list)
+ true
+
+ /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
+ PE_DEBUGHALT();
+
+
+
+ UserInitFeatureGrp
+ false
+ true
+
+
+ UserInitGrp
+ false
+ true
+ true
+
+
+ EntryPoint_UserDecl
+ false
+ (string list)
+ true
+
+
+
+ EntryPoint_UserCodeBefore
+ false
+ (string list)
+ true
+
+
+
+ EntryPoint_UserCodeAfter
+ false
+ (string list)
+ true
+
+
+
+ NotSdk0
+ false
+ true
+
+
+ Cmplr_GenerateDebuggerFiles
+ false
+ false
+ true
+ true
+ true
+
+
+ Cmplr_GenerateCfgFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_GenerateMemFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_GenerateXmlFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_AddStartupCond
+ false
+ true
+
+
+ NotSDK
+ false
+ true
+
+
+ Cmplr_AddStartupGrp
+ false
+ true
+ true
+
+
+ Cmplr_AddStartup
+ false
+ false
+ true
+ 0
+ true
+
+
+ C_GenerateLINKFILE
+ false
+ false
+ true
+ true
+ true
+
+
+ InitializationState
+ false
+ Force_SetDefault
+ true
+
+
+ InterruptVectorTableSizeAdjustment
+ false
+ false
+ 0
+ true
+ DEC
+
+
+ C_StackSize
+ false
+ false
+ 1024
+ true
+ HEX
+
+
+ C_HeapSize
+ false
+ false
+ 0
+ true
+ HEX
+
+
+ DefaultMemAreas
+ false
+ Click to set default >
+ true
+
+
+ C_AlraedyInitialized
+ false
+ false
+ true
+ 1
+ false
+
+
+ SdkSettingsGrp
+ false
+ true
+
+
+ VectorTableCopyRam
+ false
+ false
+ true
+ 0
+ true
+
+
+ DefaultMemInterrupts
+ false
+ false
+ true
+ 0
+ INTERNAL_RAM
+
+
+ DefaultMemCode
+ false
+ false
+ true
+ 0
+ INTERNAL_RAM
+
+
+ DefaultMemData
+ false
+ false
+ true
+ 0
+ INTERNAL_RAM
+
+
+ C_RomRamList
+ false
+ 5
+ true
+ true
+
+
+ C_MemoryArea0
+ false
+ true
+ true
+
+
+ C_RomRamArea0
+ false
+ false
+ true
+ true
+ true
+
+
+ C_RomRamName0
+ false
+ m_interrupts
+ true
+
+
+ C_RomRamQualifier0
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType0
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr0
+ false
+ false
+ 0
+ true
+ HEX
+
+
+
+ C_RomRamSize0
+ false
+ false
+ 488
+ true
+ HEX
+
+
+ C_RomRamGroupContent0
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea1
+ false
+ true
+ true
+
+
+ C_RomRamArea1
+ false
+ false
+ true
+ false
+ true
+
+
+ C_RomRamName1
+ false
+ m_text_000001E8
+ true
+
+
+ C_RomRamQualifier1
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType1
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr1
+ false
+ false
+ 488
+ true
+ HEX
+
+
+
+ C_RomRamSize1
+ false
+ false
+ 536
+ true
+ HEX
+
+
+ C_RomRamGroupContent1
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea2
+ false
+ true
+ true
+
+
+ C_RomRamArea2
+ false
+ false
+ true
+ true
+ true
+
+
+ C_RomRamName2
+ false
+ m_text
+ true
+
+
+ C_RomRamQualifier2
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType2
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr2
+ false
+ false
+ 1040
+ true
+ HEX
+
+
+
+ C_RomRamSize2
+ false
+ false
+ 1047536
+ true
+ HEX
+
+
+ C_RomRamGroupContent2
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea3
+ false
+ true
+ true
+
+
+ C_RomRamArea3
+ false
+ false
+ true
+ true
+ false
+
+
+ C_RomRamName3
+ false
+ m_data
+ true
+
+
+ C_RomRamQualifier3
+ false
+ false
+ true
+ 2
+ RW
+
+
+ C_RomRamPhysicalType3
+ false
+ RAM
+ true
+
+
+ C_RomRamAddr3
+ false
+ false
+ 536805376
+ true
+ HEX
+
+
+
+ C_RomRamSize3
+ false
+ false
+ 65536
+ true
+ HEX
+
+
+ C_RomRamGroupContent3
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea4
+ false
+ true
+ true
+
+
+ C_RomRamArea4
+ false
+ false
+ true
+ true
+ false
+
+
+ C_RomRamName4
+ false
+ m_data_20000000
+ true
+
+
+ C_RomRamQualifier4
+ false
+ false
+ true
+ 2
+ RW
+
+
+ C_RomRamPhysicalType4
+ false
+ RAM
+ true
+
+
+ C_RomRamAddr4
+ false
+ false
+ 536870912
+ true
+ HEX
+
+
+
+ C_RomRamSize4
+ false
+ false
+ 65536
+ true
+ HEX
+
+
+ C_RomRamGroupContent4
+ false
+ (string list)
+ true
+
+
+
+ C_PECompilerSupportCondGrp
+ false
+ true
+
+
+ C_PECompilerSupport
+ false
+ true
+ true
+
+
+ C_ToolDir
+ false
+ C:\CodeWarrior for ColdFire V7.0\
+ true
+
+
+ C_GenerateMAKEFILE
+ false
+ false
+ true
+ 0
+ true
+
+
+ asmgrp
+ false
+ true
+ true
+
+
+ C_DebugInfo
+ false
+ false
+ true
+ 0
+ true
+
+
+ C_CCPars
+ false
+
+ true
+
+
+ lnkgrp
+ false
+ true
+ true
+
+
+ C_GenerateMapFile
+ false
+ false
+ true
+ true
+ true
+
+
+ C_GenerateMapFile_ListClosure
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateMapFile_ListUnusedObjects
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateMapFile_ListDWARFObjects
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateSFile
+ false
+ false
+ true
+ true
+ true
+
+
+ C_GenerateSFile_Sort
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateSFile_MaxLength
+ false
+ false
+ 26
+ true
+ DEC
+
+
+ C_GenerateSFile_EOL
+ false
+ false
+ true
+ 1
+ DOS
+
+
+ C_LINKPars
+ false
+
+ true
+
+
+ NonECLIGrp
+ false
+ true
+
+
+ SystemPathsGrp
+ false
+ 0
+ true
+ true
+
+
+ UserPathsGrp
+ false
+ 0
+ true
+ false
+
+
+ LibrariesGrp
+ false
+ 0
+ true
+ false
+
+
+ UserDirectoriesGrp
+ false
+ 0
+ true
+ false
+
+
+ GNUC_ARM_Directory
+ false
+ true
+
+
+ Ansi-C
+ 0
+ HEX
+ HEX
+ HEX
+ HEX
+
+ MK70FN1M0VMJ12
+ 4
+ 32.768000000000
+
+
+
+
+
+
+
+ file:/${ProcessorExpert_loc}/Repositories/Kinetis_Repository
+ com.freescale.processorexpert.processor.mk70fn1m0mj15
+ MK70FN1M0MJ15
+ Cpu
+ 4
+ true
+ ALWAYS_WRITE
+ CPU_CHIP2
+
+
+
+ 01.028
+ false
+
+
+ DeviceName
+ false
+ false
+ Cpu
+
+
+ CPU
+ false
+ false
+ MK70FN1M0VMJ12
+
+
+ SharedInternalProperties
+ 1
+
+
+ SharedInternalPropertiesGrp
+ false
+ false
+ false
+
+
+ CPU_peripheral
+ false
+ false
+ CPU
+ false
+
+
+ MemModelDev
+ false
+ false
+ MemModel_NoFlexMem
+ false
+
+
+ Shared_ClockSettings
+ 1
+
+
+ ClockSettingGrp
+ false
+ false
+ false
+
+
+ ICLK
+ false
+ false
+ true
+
+
+ IntOsc
+ false
+ false
+ false
+ 32.768
+
+
+ InitializeSlowTRIM
+ false
+ false
+ false
+ false
+ false
+
+
+ SlowTRIMvalueAddress
+ false
+ false
+ false
+ 1023
+ HEX
+
+
+
+ SlowFTRIMvalueAddress
+ false
+ false
+ false
+ 1022
+ HEX
+
+
+
+ IntOscFast
+ false
+ false
+ false
+ 4
+
+
+ InitializeFastTRIM
+ false
+ false
+ false
+ false
+ false
+
+
+ FastTRIMvalueAddress
+ false
+ false
+ false
+ 1022
+ HEX
+
+
+
+ RTCOSCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ RTCOSC
+ false
+ false
+ false
+ 0.032768
+
+
+ RTCOSC_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ SystemOSCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SystemOSCSrc
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSCExtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSCExtalPin
+
+ false
+
+
+ SystemOSCExtalPinSignal
+ false
+ false
+
+
+
+ SystemOSCXtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSCXtalPin
+
+ false
+
+
+ SystemOSCXtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC
+ false
+ false
+ false
+ 8
+
+
+ SystemOSC_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ExtOscOperatingMode
+ false
+ false
+ false
+ 1
+ 0
+
+
+ SystemOSC1Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ SystemOSC1Src
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSC1Extal_Grp
+ false
+ false
+ true
+
+
+ SystemOSC1ExtalPin
+
+ false
+
+
+ SystemOSC1ExtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC1Xtal_Grp
+ false
+ false
+ true
+
+
+ SystemOSC1XtalPin
+
+ false
+
+
+ SystemOSC1XtalPinSignal
+ false
+ false
+
+
+
+ SystemOSC1
+ false
+ false
+ false
+ 8
+
+
+ SystemOSC1_CapacitorLoad
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ExtOsc1OperatingMode
+ false
+ false
+ false
+ 1
+ 0
+
+
+ CLKModeList
+ false
+ 1
+ false
+ true
+
+
+ CLKMode0
+ false
+ false
+ true
+
+
+ IRCLKGrp0
+ false
+ false
+ false
+
+
+ IRCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ IREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ IRCLKSelectCLKMode0
+ false
+ false
+ false
+ 0
+ false
+
+
+ FCRDIVCLKMode0
+ false
+ true
+ 1
+ 1
+
+
+ IRCLKClkCLKMode0
+ false
+ 0.032768
+
+
+ ERCLKGrp0
+ false
+ false
+ false
+
+
+ SystemOSCERCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSCEREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ ERCLKClkCLKMode0
+ false
+ 0
+
+
+ SystemOSC1ERCLKENCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ SystemOSC1EREFSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ ERCLK1ClkCLKMode0
+ false
+ 0
+
+
+ ERCLK32KSelectCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ ERCLK32KClkCLKMode0
+ false
+ 0
+
+
+ MCGGrp0
+ false
+ false
+ true
+
+
+ MCGModeSelCLKMode0
+ false
+ false
+ false
+ 0
+
+
+ PLLCSCLKMode0
+ false
+ false
+ false
+ true
+ 0
+ 0
+
+
+ MCGOUTSelectCLKMode0
+ false
+ 0
+ FLLOUT
+
+
+ MCGModeCLKMode0
+
+
+
+ MCGOutputCLKMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ MCG_ERCLKSelectCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ MCG_ERCLKClkCLKMode0
+ false
+ 0
+
+
+ ClockMonitorGrp0
+ false
+ false
+ true
+
+
+ MCGCMECLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ MCGCME1CLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ MCGCME2CLKMode0
+ false
+ false
+ false
+ 1
+ 0
+
+
+ FLLGrp0
+ false
+ false
+ true
+
+
+ FLLEnblCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ FLLOutputCLKMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ FLLFixedClkCLKMode0
+ false
+ 16.384
+
+
+ FLL_RefClkSrcCLKMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ MCG_FRDIV_CLKMode0
+ false
+ false
+ false
+ true
+ 0
+ Auto select
+
+
+ FLLRefClkCLKMode0
+ false
+ 32.768
+
+
+ MCG_FLL_MFactor_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLGrp0
+ false
+ false
+ true
+
+
+ PLLEnblCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLSTENCLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLREFSELCLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ PLLOutputCLKMode0
+ false
+ false
+ false
+ 120
+
+
+ MCG_PRDIV_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLRefClkCLKMode0
+ false
+ 1
+
+
+ MCG_VDIV_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLL_LOLIECLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLL1Grp0
+ false
+ false
+ true
+
+
+ PLLEnbl1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLSTEN1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ PLLOutput1CLKMode0
+ false
+ false
+ false
+ 120
+
+
+ PLLREFSEL1CLKMode0
+ false
+ false
+ false
+ 0
+ 0
+
+
+ MCG_PRDIV1_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLLRefClk1CLKMode0
+ false
+ 1
+
+
+ MCG_VDIV1_CLKMode0
+ false
+ false
+ false
+ 0
+ Auto select
+
+
+ PLL_LOLIE1CLKMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ InitPriority
+ false
+ false
+ minimal priority
+
+
+ WDOGDis
+ false
+ false
+ false
+ 0
+ true
+
+
+ Intperiphgrp
+ false
+ false
+ false
+
+
+ SharedADC0
+ 1
+
+
+ ADCGrp
+ false
+ false
+ false
+
+
+ ADCCondGrp
+ false
+ false
+
+
+ ADCAsynchroClock
+ false
+ false
+ false
+ Auto select
+ true
+
+
+ ADC0CondGrp
+ false
+ false
+
+
+ ADC0AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC1CondGrp
+ false
+ false
+
+
+ ADC1AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC2CondGrp
+ false
+ false
+
+
+ ADC2AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC3CondGrp
+ false
+ false
+
+
+ ADC3AsynchroClock
+ false
+ false
+ false
+ Auto select
+
+
+ ADC4CondGrp
+ false
+ false
+
+
+ ADC4AsynchroClock
+ false
+ false
+ false
+ Auto select
+ true
+
+
+ DisNMINMIPin
+ false
+ false
+ TSI0_CH5/PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b
+ false
+
+
+ SharedNMI
+ 1
+
+
+ NMINMIPinEn
+ false
+ false
+ false
+ false
+ false
+
+
+ NMINMIPin
+ false
+ false
+ TSI0_CH5/PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b
+ false
+
+
+ NMINMIPinSignal
+ false
+ false
+
+
+
+ SharedNMI0
+ 1
+
+
+ RCMGrp
+ false
+ false
+ false
+ true
+ false
+
+
+ PeriphDeviceRCM
+ false
+ false
+ RCM
+ false
+
+
+ RCMResetPin
+ false
+ false
+ RESET_b
+ false
+
+
+ RCMResetPinSignal
+ false
+ false
+
+
+
+ RCMFilterInStop
+ false
+ false
+ false
+ typeKinetisRCMFilterInStop
+ 0
+ disabled
+
+
+ RCMFilterInRunWait
+ false
+ false
+ false
+ typeKinetisRCMFilterInRunWait
+ 0
+ disabled
+
+
+ RCMFilterWidth
+ false
+ false
+ false
+ 1
+ DEC
+
+
+ RCMInternalUsageGrp
+ false
+ false
+ true
+
+
+ RCMIsInitialized
+ false
+ 0
+ true
+
+
+ SharedJTAG
+ 1
+
+
+ JTAGGrp
+ false
+ false
+ false
+
+
+ JTAGMode
+ false
+ false
+ false
+ 0
+ true
+
+
+ JTAGTDIPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTDIPin
+ false
+ false
+ TSI0_CH2/PTA1/UART0_RX/FTM0_CH6/JTAG_TDI/EZP_DI
+ false
+
+
+ JTAGTDIPinSignal
+ false
+ false
+
+
+
+ JTAGTDOPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTDOPin
+ false
+ false
+ TSI0_CH3/PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO
+ false
+
+
+ JTAGTDOPinSignal
+ false
+ false
+
+
+
+ JTAGTCKPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTCKPin
+ false
+ false
+ TSI0_CH1/PTA0/UART0_CTS_b/UART0_COL_b/FTM0_CH5/JTAG_TCLK/SWD_CLK/EZP_CLK
+ false
+
+
+ JTAGTCKPinSignal
+ false
+ false
+
+
+
+ JTAGTMSPinEn
+ false
+ false
+ false
+ true
+ true
+
+
+ JTAGTMSPin
+ false
+ false
+ TSI0_CH4/PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO
+ false
+
+
+ JTAGTMSPinSignal
+ false
+ false
+
+
+
+ JTAGnTRSTPinEn
+ false
+ false
+ false
+ false
+ false
+
+
+ JTAGnTRSTPin
+ false
+ false
+
+ false
+
+
+ JTAGnTRSTPinSignal
+ false
+ false
+
+
+
+ SharedFlashOrganization
+ 1
+
+
+ FlashMemoryOrgGrp
+ false
+ false
+ true
+
+
+ SharedFLASHGrp
+ 1
+
+
+ FlexNVMCondGrp
+ false
+ false
+
+
+ FlexNVMSettings
+ false
+ false
+ true
+ true
+
+
+ FlexNVMComponentVersion
+ false
+ false
+
+ true
+
+
+ EEEpart
+ false
+ false
+ false
+ true
+ 10
+ 16384
+
+
+ Dpart
+ false
+ false
+ false
+ true
+ 17
+ 512
+
+
+ FlexNVMSize_Txt
+
+ true
+
+
+ DataFlashSize_KB_Txt
+ 0 KB
+ true
+
+
+ FlexNVMPartitionCodeValue
+ false
+ false
+
+ true
+
+
+ EepromSize_Enum
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ EepromSplitFactorCondGrp
+ false
+ false
+ true
+
+
+ EepromSplitFactor
+ false
+ false
+ false
+ true
+ 2
+ 2
+
+
+ EepromBackupSize_KB_Enum
+ false
+ false
+ false
+ true
+ 0
+ 8
+
+
+ DflashSettingsGrp
+ false
+ false
+ true
+ true
+
+
+ DataFlashStart
+ false
+ 268435456
+ true
+ HEX
+
+
+ DataFlashSize
+ false
+ 0
+ true
+ HEX
+
+
+ EepromBackupSettingsGrp
+ false
+ false
+ true
+ true
+
+
+ EepromBackupStart
+ false
+ 268435456
+ true
+ HEX
+
+
+ EepromBackupSize
+ false
+ 0
+ true
+ HEX
+
+
+ EepromDataSettingsGrp
+ false
+ false
+ true
+ true
+
+
+ EepromStart
+ false
+ 335544320
+ true
+ HEX
+
+
+ EepromSize
+ false
+ 0
+ true
+ HEX
+
+
+ FlexRAM
+ false
+ false
+ false
+ true
+ false
+ false
+
+
+ FlexRAMStart
+ false
+ 335544320
+ true
+ HEX
+
+
+ FlexRAMSize
+ false
+ 0
+ true
+ DEC
+
+
+ EEEFeatureIsInitialized
+ false
+ true
+ 1
+ false
+
+
+ 4
+ FlashOrgDscrBlockList
+ true
+
+
+ FlashOrgDscrBlock0
+ false
+ false
+ true
+
+
+ FlashOrgDscrBlockAddress0
+ false
+ 0
+ HEX
+
+
+ FlashOrgDscrBlockSize0
+ false
+ 262144
+ DEC
+
+
+ FlashOrgDscrBlockWUnitSize0
+ false
+ 8
+ DEC
+
+
+ FlashOrgDscrBlockEUnitSize0
+ false
+ 4096
+ DEC
+
+
+ FlashOrgDscrBlockPUnitSize0
+ false
+ 32768
+ DEC
+
+
+ FlashOrgDscrBlock1
+ false
+ false
+ true
+
+
+ FlashOrgDscrBlockAddress1
+ false
+ 262144
+ HEX
+
+
+ FlashOrgDscrBlockSize1
+ false
+ 262144
+ DEC
+
+
+ FlashOrgDscrBlockWUnitSize1
+ false
+ 8
+ DEC
+
+
+ FlashOrgDscrBlockEUnitSize1
+ false
+ 4096
+ DEC
+
+
+ FlashOrgDscrBlockPUnitSize1
+ false
+ 32768
+ DEC
+
+
+ FlashOrgDscrBlock2
+ false
+ false
+ true
+
+
+ FlashOrgDscrBlockAddress2
+ false
+ 524288
+ HEX
+
+
+ FlashOrgDscrBlockSize2
+ false
+ 262144
+ DEC
+
+
+ FlashOrgDscrBlockWUnitSize2
+ false
+ 8
+ DEC
+
+
+ FlashOrgDscrBlockEUnitSize2
+ false
+ 4096
+ DEC
+
+
+ FlashOrgDscrBlockPUnitSize2
+ false
+ 32768
+ DEC
+
+
+ FlashOrgDscrBlock3
+ false
+ false
+ true
+
+
+ FlashOrgDscrBlockAddress3
+ false
+ 786432
+ HEX
+
+
+ FlashOrgDscrBlockSize3
+ false
+ 262144
+ DEC
+
+
+ FlashOrgDscrBlockWUnitSize3
+ false
+ 8
+ DEC
+
+
+ FlashOrgDscrBlockEUnitSize3
+ false
+ 4096
+ DEC
+
+
+ FlashOrgDscrBlockPUnitSize3
+ false
+ 32768
+ DEC
+
+
+ ShrdPFLASHGrp
+ 1
+
+
+ FMCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceFMC
+ false
+ false
+
+ false
+
+
+ FMCProtGrp
+ false
+ false
+ false
+
+
+ FMCMaster0_Grp
+ false
+ false
+ false
+
+
+ FMCMaster0Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 0
+ enabled
+
+
+ FMCMaster0AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 3
+ read_write
+
+
+ FMCMaster1_Grp
+ false
+ false
+ false
+
+
+ FMCMaster1Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 0
+ enabled
+
+
+ FMCMaster1AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 3
+ read_write
+
+
+ FMCMaster2_Grp
+ false
+ false
+ false
+
+
+ FMCMaster2Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 0
+ enabled
+
+
+ FMCMaster2AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 3
+ read_write
+
+
+ FMCMaster3_Grp
+ false
+ false
+ false
+
+
+ FMCMaster3Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 1
+ disabled
+
+
+ FMCMaster3AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 0
+ no_access
+
+
+ FMCMaster4_Grp
+ false
+ false
+ false
+
+
+ FMCMaster4Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 1
+ disabled
+
+
+ FMCMaster4AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 0
+ no_access
+
+
+ FMCMaster5_Grp
+ false
+ false
+ false
+
+
+ FMCMaster5Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 1
+ disabled
+
+
+ FMCMaster5AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 0
+ no_access
+
+
+ FMCMaster6_Grp
+ false
+ false
+ false
+
+
+ FMCMaster6Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 1
+ disabled
+
+
+ FMCMaster6AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 0
+ no_access
+
+
+ FMCMaster7_Grp
+ false
+ false
+ false
+
+
+ FMCMaster7Prefetch
+ false
+ false
+ false
+ typeKinetisFMCMasterPrefetch
+ 1
+ disabled
+
+
+ FMCMaster7AccessProtection
+ false
+ false
+ false
+ typeKinetisFMCMasterAccessProtection
+ 0
+ no_access
+
+
+ FMCCacheGrp
+ false
+ false
+ false
+
+
+ FMCBank0_Grp
+ false
+ false
+ false
+
+
+ FMCBank0ReplacementCtrl
+ false
+ false
+ false
+ typeKinetisFMCBankReplacementCtrl
+ 0
+ 0
+
+
+ FMCBank0DCE
+ false
+ false
+ false
+ typeKinetisFMCBankDCE
+ 0
+ enabled
+
+
+ FMCBank0ICE
+ false
+ false
+ false
+ typeKinetisFMCBankICE
+ 0
+ enabled
+
+
+ FMCBank0DPE
+ false
+ false
+ false
+ typeKinetisFMCBankDPE
+ 0
+ enabled
+
+
+ FMCBank0IPE
+ false
+ false
+ false
+ typeKinetisFMCBankIPE
+ 0
+ enabled
+
+
+ FMCBank0PBE
+ false
+ false
+ false
+ typeKinetisFMCBankPBE
+ 0
+ enabled
+
+
+ FMCBank1_Grp
+ false
+ false
+ false
+
+
+ FMCBank1DCE
+ false
+ false
+ false
+ typeKinetisFMCBankDCE
+ 0
+ enabled
+
+
+ FMCBank1ICE
+ false
+ false
+ false
+ typeKinetisFMCBankICE
+ 0
+ enabled
+
+
+ FMCBank1DPE
+ false
+ false
+ false
+ typeKinetisFMCBankDPE
+ 0
+ enabled
+
+
+ FMCBank1IPE
+ false
+ false
+ false
+ typeKinetisFMCBankIPE
+ 0
+ enabled
+
+
+ FMCBank1PBE
+ false
+ false
+ false
+ typeKinetisFMCBankPBE
+ 0
+ enabled
+
+
+ FMCInternalUsageGrp
+ false
+ false
+ true
+
+
+ FMCIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdFLASHCfgGrp
+ 1
+
+
+ FTFL_FlashConfigGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ PeriphDeviceFTFL_FlashConfig
+ false
+ false
+ FTFE_FlashConfig
+ false
+
+
+ FTFL_FlashConfigSecuritySettingsGrp
+ false
+ false
+ false
+
+
+ FTFL_FlashConfigSecurity
+ false
+ false
+ false
+ false
+ false
+
+
+ FTFL_FlashConfigSecureValue
+ false
+ false
+ false
+ typeKinetisFTFL_FlashConfigSecureValue
+ 0
+ 00
+
+
+ FTFL_FlashConfigFslAccess
+ false
+ false
+ false
+ typeKinetisFTFL_FlashConfigFslAccess
+ 0
+ granted
+
+
+ FTFL_FlashConfigMassEraseEnable
+ false
+ false
+ false
+ typeKinetisFTFL_FlashConfigMassEraseEnable
+ 0
+ enabled
+
+
+ FTFL_FlashConfigBackdoorkeyEnable
+ false
+ false
+ false
+ typeKinetisFTFL_FlashConfigBackdoorkeyEnable
+ 1
+ disabled
+
+
+ FTFL_FlashConfigBackdoorKey0
+ false
+ false
+ false
+ 255
+ DEC
+
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+ MPURegionValid15
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+ MPUStartAddress15
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+ MPUEndAddress15
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+ MPUMaster0Grp15
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+ MPUInternalUsageGrp
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+ MPUIsInitialized
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+ ShrdAXBSGrp
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+
+ AXBSGrp
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+ PeriphDeviceAXBS
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+ AXBSBusSlave0_Flash_Grp
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+ AXBSBusSlave0_Flash_Master0_CORE_CODE
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+ AXBSBusSlave0_Flash_Master2_DMA_EzPort
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+ AXBSBusSlave0_Flash_Master3_SDHC_NFC_USB
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+
+
+ AXBSBusSlave0_Flash_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave0_Flash_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave0_Flash_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave0_Flash_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave0_Flash_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave0_Flash_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave0_Flash_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave0_Flash_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave0_Flash_HLP
+ 0
+ high
+
+
+ AXBSBusSlave1_SRAM_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave1_SRAM_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave1_SRAM_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave1_SRAM_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave1_SRAM_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave1_SRAM_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave1_SRAM_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave1_SRAM_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave1_SRAM_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave1_SRAM_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave1_SRAM_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave1_SRAM_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave1_SRAM_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave1_SRAM_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave1_SRAM_HLP
+ 0
+ high
+
+
+ AXBSBusSlave2_PBRIDGE0_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave2_PBRIDGE0_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave2_PBRIDGE0_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave2_PBRIDGE0_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave2_PBRIDGE0_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave2_PBRIDGE0_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave2_PBRIDGE0_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave2_PBRIDGE0_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave2_PBRIDGE0_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave2_PBRIDGE0_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave2_PBRIDGE0_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave2_PBRIDGE0_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave2_PBRIDGE0_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave2_PBRIDGE0_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave2_PBRIDGE0_HLP
+ 0
+ high
+
+
+ AXBSBusSlave3_PBRIDGE1_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave3_PBRIDGE1_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave3_PBRIDGE1_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave3_PBRIDGE1_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave3_PBRIDGE1_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave3_PBRIDGE1_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave3_PBRIDGE1_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave3_PBRIDGE1_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave3_PBRIDGE1_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave3_PBRIDGE1_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave3_PBRIDGE1_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave3_PBRIDGE1_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave3_PBRIDGE1_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave3_PBRIDGE1_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave3_PBRIDGE1_HLP
+ 0
+ high
+
+
+ AXBSBusSlave4_FLEXBUS_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave4_FLEXBUS_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave4_FLEXBUS_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave4_FLEXBUS_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave4_FLEXBUS_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave4_FLEXBUS_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave4_FLEXBUS_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave4_FLEXBUS_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave4_FLEXBUS_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave4_FLEXBUS_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave4_FLEXBUS_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave4_FLEXBUS_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave4_FLEXBUS_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave4_FLEXBUS_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave4_FLEXBUS_HLP
+ 0
+ high
+
+
+ AXBSBusSlave5_DDR0_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave5_DDR0_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave5_DDR0_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave5_DDR0_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave5_DDR0_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave5_DDR0_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave5_DDR0_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave5_DDR0_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave5_DDR0_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave5_DDR0_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave5_DDR0_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave5_DDR0_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave5_DDR0_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave5_DDR0_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave5_DDR0_HLP
+ 0
+ high
+
+
+ AXBSBusSlave6_DDR1_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave6_DDR1_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave6_DDR1_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave6_DDR1_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave6_DDR1_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave6_DDR1_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave6_DDR1_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave6_DDR1_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave6_DDR1_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave6_DDR1_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave6_DDR1_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave6_DDR1_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave6_DDR1_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave6_DDR1_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave6_DDR1_HLP
+ 0
+ high
+
+
+ AXBSBusSlave7_DDR2_Grp
+ false
+ false
+ false
+
+
+ AXBSBusSlave7_DDR2_PriGrp
+ false
+ false
+ true
+
+
+ AXBSBusSlave7_DDR2_Master0_CORE_CODE
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 0
+ P1
+
+
+ AXBSBusSlave7_DDR2_Master1_CORE_SYSTEM
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 1
+ P2
+
+
+ AXBSBusSlave7_DDR2_Master2_DMA_EzPort
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 2
+ P3
+
+
+ AXBSBusSlave7_DDR2_Master3_SDHC_NFC_USB
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 3
+ P4
+
+
+ AXBSBusSlave7_DDR2_Master4_LCDC_BUS0
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 4
+ P5
+
+
+ AXBSBusSlave7_DDR2_Master5_LCDC_BUS1
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 5
+ P6
+
+
+ AXBSBusSlave7_DDR2_Master6_USBHS
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 6
+ P7
+
+
+ AXBSBusSlave7_DDR2_Master7_ENET
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Master_
+ 7
+ P8
+
+
+ AXBSBusSlave7_DDR2_ArbMode
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_ArbMode
+ 0
+ Fixed_priority
+
+
+ AXBSBusSlave7_DDR2_Parking
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_Parking
+ 0
+ Master0
+
+
+ AXBSBusSlave7_DDR2_ReadOnly
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_ReadOnly
+ 1
+ No
+
+
+ AXBSBusSlave7_DDR2_HLP
+ false
+ false
+ false
+ typeKinetisAXBSBusSlave7_DDR2_HLP
+ 0
+ high
+
+
+ AXBSMastersArbitr_Grp
+ false
+ false
+ false
+
+
+ AXBSBusMasterSettingsGrp0
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB0
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp1
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB1
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp2
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB2
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp3
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB3
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp4
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB4
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp5
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB5
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp6
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB6
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSBusMasterSettingsGrp7
+ false
+ false
+ false
+
+
+ AXBSBusMasterAULB7
+ false
+ false
+ false
+ typeKinetisAXBSBusMasterAULB
+ 0
+ notAllowed
+
+
+ AXBSInternalUsageGrp
+ false
+ false
+ true
+
+
+ AXBSIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdAIPS0Grp
+ 1
+
+
+ AIPS0Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceAIPS0
+ false
+ false
+
+ false
+
+
+ AIPS0BusMasterGrp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_CODE_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_CODE_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_CODE_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_CODE_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_CORE_SYSTEM_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_CORE_SYSTEM_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_DMA_EzPort_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS0BusMaster_DMA_EzPort_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS0BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_Grp
+ false
+ false
+ false
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_TrustedRead
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+ typeKinetisAIPS0BusMaster__TrustedRead
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+ no
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_TrustedWrite
+ false
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+ no
+
+
+ AIPS0BusMaster_SDHC_NFC_USB_PrivilegeLevel
+ false
+ false
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+ no
+
+
+ AIPS0BusMaster_LCDC_BUS0_Grp
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+
+
+ AIPS0BusMaster_LCDC_BUS0_TrustedRead
+ false
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+
+ AIPS0BusMaster_LCDC_BUS0_TrustedWrite
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+
+ AIPS0BusMaster_LCDC_BUS0_PrivilegeLevel
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+
+ AIPS0BusMaster_LCDC_BUS1_Grp
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+
+ AIPS0BusMaster_LCDC_BUS1_TrustedRead
+ false
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+
+
+ AIPS0BusMaster_LCDC_BUS1_TrustedWrite
+ false
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+ no
+
+
+ AIPS0BusMaster_LCDC_BUS1_PrivilegeLevel
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+
+
+ AIPS0BusMaster_USBHS_Grp
+ false
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+ false
+
+
+ AIPS0BusMaster_USBHS_TrustedRead
+ false
+ false
+ false
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+
+
+ AIPS0BusMaster_USBHS_TrustedWrite
+ false
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+
+
+ AIPS0BusMaster_USBHS_PrivilegeLevel
+ false
+ false
+ false
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+
+
+ AIPS0BusMaster_ENET_Grp
+ false
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+ false
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+
+ AIPS0BusMaster_ENET_TrustedRead
+ false
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+
+ AIPS0BusMaster_ENET_TrustedWrite
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+ 1
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+
+
+ AIPS0BusMaster_ENET_PrivilegeLevel
+ false
+ false
+ false
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+ 1
+ no
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+
+ AIPS0PeripheralAccessControlGrp
+ false
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+ false
+
+
+ AIPS0PrphAccessGrp_AIPS0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_AIPS0_SupervisorProtect
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+
+ AIPS0PrphAccess_AIPS0_WriteProtect
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+
+ AIPS0PrphAccess_AIPS0_TrustedProtect
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+
+ AIPS0PrphAccessGrp_AXBS
+ false
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+
+
+ AIPS0PrphAccess_AXBS_SupervisorProtect
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+
+ AIPS0PrphAccess_AXBS_WriteProtect
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+
+ AIPS0PrphAccess_AXBS_TrustedProtect
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+
+ AIPS0PrphAccessGrp_DMA
+ false
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+
+ AIPS0PrphAccess_DMA_SupervisorProtect
+ false
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+
+ AIPS0PrphAccess_DMA_WriteProtect
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+
+ AIPS0PrphAccess_DMA_TrustedProtect
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+ false
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+
+
+ AIPS0PrphAccessGrp_DMA_DESCRIPTORS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_SupervisorProtect
+ false
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+ false
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+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_WriteProtect
+ false
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+
+
+ AIPS0PrphAccess_DMA_DESCRIPTORS_TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_FB
+ false
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+ false
+
+
+ AIPS0PrphAccess_FB_SupervisorProtect
+ false
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+
+ AIPS0PrphAccess_FB_WriteProtect
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+
+ AIPS0PrphAccess_FB_TrustedProtect
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+
+ AIPS0PrphAccessGrp_MPU
+ false
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+
+
+ AIPS0PrphAccess_MPU_SupervisorProtect
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+
+ AIPS0PrphAccess_MPU_WriteProtect
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+
+ AIPS0PrphAccess_MPU_TrustedProtect
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+
+ AIPS0PrphAccessGrp_FMC
+ false
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+
+
+ AIPS0PrphAccess_FMC_SupervisorProtect
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+
+ AIPS0PrphAccess_FMC_WriteProtect
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+
+ AIPS0PrphAccess_FMC_TrustedProtect
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+
+ AIPS0PrphAccessGrp_FTFE
+ false
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+
+
+ AIPS0PrphAccess_FTFE_SupervisorProtect
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+
+ AIPS0PrphAccess_FTFE_WriteProtect
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+
+ AIPS0PrphAccess_FTFE_TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_DMA_MULTIPLEXOR0
+ false
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+ false
+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_SupervisorProtect
+ false
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+ typeKinetisAIPS0PrphAccess__SupervisorProtect
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+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_WriteProtect
+ false
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+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR0_TrustedProtect
+ false
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+
+
+ AIPS0PrphAccessGrp_DMA_MULTIPLEXOR1
+ false
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+
+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_SupervisorProtect
+ false
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+ typeKinetisAIPS0PrphAccess__SupervisorProtect
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+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_WriteProtect
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+
+ AIPS0PrphAccess_DMA_MULTIPLEXOR1_TrustedProtect
+ false
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+
+ AIPS0PrphAccessGrp_CAN0
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+
+
+ AIPS0PrphAccess_CAN0_SupervisorProtect
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+
+ AIPS0PrphAccess_CAN0_WriteProtect
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+
+ AIPS0PrphAccess_CAN0_TrustedProtect
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+
+ AIPS0PrphAccessGrp_SPI0
+ false
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+
+
+ AIPS0PrphAccess_SPI0_SupervisorProtect
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+
+ AIPS0PrphAccess_SPI0_WriteProtect
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+
+ AIPS0PrphAccess_SPI0_TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_SPI1
+ false
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+
+
+ AIPS0PrphAccess_SPI1_SupervisorProtect
+ false
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+
+ AIPS0PrphAccess_SPI1_WriteProtect
+ false
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+
+ AIPS0PrphAccess_SPI1_TrustedProtect
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+
+ AIPS0PrphAccessGrp_I2S0
+ false
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+
+
+ AIPS0PrphAccess_I2S0_SupervisorProtect
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+
+ AIPS0PrphAccess_I2S0_WriteProtect
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+
+ AIPS0PrphAccess_I2S0_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
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+
+ AIPS0PrphAccessGrp_I2S1
+ false
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+
+
+ AIPS0PrphAccess_I2S1_SupervisorProtect
+ false
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+
+
+ AIPS0PrphAccess_I2S1_WriteProtect
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+
+
+ AIPS0PrphAccess_I2S1_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_CRC
+ false
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+
+
+ AIPS0PrphAccess_CRC_SupervisorProtect
+ false
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+
+ AIPS0PrphAccess_CRC_WriteProtect
+ false
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+ 1
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+
+ AIPS0PrphAccess_CRC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_USBHS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_USBHS_SupervisorProtect
+ false
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+ false
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+
+
+ AIPS0PrphAccess_USBHS_WriteProtect
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+ 1
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+
+ AIPS0PrphAccess_USBHS_TrustedProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_USBDCD
+ false
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+ false
+
+
+ AIPS0PrphAccess_USBDCD_SupervisorProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
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+
+
+ AIPS0PrphAccess_USBDCD_WriteProtect
+ false
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+ 1
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+
+
+ AIPS0PrphAccess_USBDCD_TrustedProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_PDB0
+ false
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+ false
+
+
+ AIPS0PrphAccess_PDB0_SupervisorProtect
+ false
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+ typeKinetisAIPS0PrphAccess__SupervisorProtect
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+
+
+ AIPS0PrphAccess_PDB0_WriteProtect
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+ 1
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+
+
+ AIPS0PrphAccess_PDB0_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_PIT
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PIT_SupervisorProtect
+ false
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+ false
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+ 1
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+
+
+ AIPS0PrphAccess_PIT_WriteProtect
+ false
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+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
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+
+
+ AIPS0PrphAccess_PIT_TrustedProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_FTM0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_FTM0_SupervisorProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
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+
+
+ AIPS0PrphAccess_FTM0_WriteProtect
+ false
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+ 1
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+
+
+ AIPS0PrphAccess_FTM0_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_FTM1
+ false
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+ false
+
+
+ AIPS0PrphAccess_FTM1_SupervisorProtect
+ false
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+ false
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+ 1
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+
+
+ AIPS0PrphAccess_FTM1_WriteProtect
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+ 1
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+
+
+ AIPS0PrphAccess_FTM1_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_ADC0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_ADC0_SupervisorProtect
+ false
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+ false
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+
+ AIPS0PrphAccess_ADC0_WriteProtect
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+
+
+ AIPS0PrphAccess_ADC0_TrustedProtect
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+ false
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+ 1
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+
+
+ AIPS0PrphAccessGrp_ADC2
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_ADC2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
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+
+
+ AIPS0PrphAccess_ADC2_WriteProtect
+ false
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+ false
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+ 1
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+
+
+ AIPS0PrphAccess_ADC2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_RTC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_RTC_SupervisorProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
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+
+
+ AIPS0PrphAccess_RTC_WriteProtect
+ false
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+ false
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+ 1
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+
+
+ AIPS0PrphAccess_RTC_TrustedProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_VBAT_REGS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_VBAT_REGS_SupervisorProtect
+ false
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+ false
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+
+
+ AIPS0PrphAccess_VBAT_REGS_WriteProtect
+ false
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+ 1
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+
+
+ AIPS0PrphAccess_VBAT_REGS_TrustedProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
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+
+
+ AIPS0PrphAccessGrp_LPTMR0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_LPTMR0_SupervisorProtect
+ false
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+ 1
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+
+
+ AIPS0PrphAccess_LPTMR0_WriteProtect
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+ 1
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+
+
+ AIPS0PrphAccess_LPTMR0_TrustedProtect
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+ 1
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+
+
+ AIPS0PrphAccessGrp_SYSTEM_REGS
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SYSTEM_REGS_SupervisorProtect
+ false
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+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
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+
+
+ AIPS0PrphAccess_SYSTEM_REGS_WriteProtect
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+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
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+
+
+ AIPS0PrphAccess_SYSTEM_REGS_TrustedProtect
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+ typeKinetisAIPS0PrphAccess__TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_TSI0
+ false
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+
+
+ AIPS0PrphAccess_TSI0_SupervisorProtect
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+
+
+ AIPS0PrphAccess_TSI0_WriteProtect
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+
+ AIPS0PrphAccess_TSI0_TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_SIM_LP
+ false
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+
+
+ AIPS0PrphAccess_SIM_LP_SupervisorProtect
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+
+
+ AIPS0PrphAccess_SIM_LP_WriteProtect
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+
+
+ AIPS0PrphAccess_SIM_LP_TrustedProtect
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+
+ AIPS0PrphAccessGrp_SIM
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+
+
+ AIPS0PrphAccess_SIM_SupervisorProtect
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+
+ AIPS0PrphAccess_SIM_WriteProtect
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+
+
+ AIPS0PrphAccess_SIM_TrustedProtect
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+
+
+ AIPS0PrphAccessGrp_PORTA
+ false
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+
+
+ AIPS0PrphAccess_PORTA_SupervisorProtect
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+
+ AIPS0PrphAccess_PORTA_WriteProtect
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+
+
+ AIPS0PrphAccess_PORTA_TrustedProtect
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+
+ AIPS0PrphAccessGrp_PORTB
+ false
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+
+
+ AIPS0PrphAccess_PORTB_SupervisorProtect
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+ false
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+
+ AIPS0PrphAccess_PORTB_WriteProtect
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+ 1
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+
+
+ AIPS0PrphAccess_PORTB_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTD
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTD_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTD_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTD_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTE
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTE_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTE_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTE_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PORTF
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PORTF_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTF_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PORTF_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_WDOG
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_WDOG_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_WDOG_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_WDOG_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_EWM
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_EWM_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_EWM_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_EWM_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CMT
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CMT_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMT_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMT_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_MCG
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_MCG_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MCG_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_MCG_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_OSC0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_OSC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_OSC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_OSC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2C0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2C0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_I2C1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_I2C1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_I2C1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART1
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART2
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_UART3
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_UART3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_UART3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_USB0
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_USB0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USB0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_USB0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_CMP
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_CMP_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMP_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_CMP_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_VREF
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_VREF_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VREF_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_VREF_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_LLWU
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_LLWU_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LLWU_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_LLWU_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_PMC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_PMC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PMC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_PMC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_SMC
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_SMC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SMC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_SMC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccessGrp_RCM
+ false
+ false
+ false
+
+
+ AIPS0PrphAccess_RCM_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RCM_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS0PrphAccess_RCM_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS0PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS0InternalUsageGrp
+ false
+ false
+ true
+
+
+ AIPS0IsInitialized
+ false
+ 1
+ false
+
+
+ ShrdAIPS1Grp
+ 1
+
+
+ AIPS1Grp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceAIPS1
+ false
+ false
+
+ false
+
+
+ AIPS1BusMasterGrp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_CODE_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_CODE_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_CODE_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_CODE_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_CORE_SYSTEM_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_CORE_SYSTEM_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_DMA_EzPort_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 0
+ yes
+
+
+ AIPS1BusMaster_DMA_EzPort_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 0
+ yes
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_SDHC_NFC_USB_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_LCDC_BUS0_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS0_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_LCDC_BUS1_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_LCDC_BUS1_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_USBHS_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_USBHS_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_Grp
+ false
+ false
+ false
+
+
+ AIPS1BusMaster_ENET_TrustedRead
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedRead
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_TrustedWrite
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__TrustedWrite
+ 1
+ no
+
+
+ AIPS1BusMaster_ENET_PrivilegeLevel
+ false
+ false
+ false
+ typeKinetisAIPS1BusMaster__PrivilegeLevel
+ 1
+ no
+
+
+ AIPS1PeripheralAccessControlGrp
+ false
+ false
+ false
+
+
+ AIPS1PrphAccessGrp_AIPS1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_AIPS1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_AIPS1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_AIPS1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_RNGA
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_RNGA_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_RNGA_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_RNGA_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_CAN1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_CAN1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_CAN1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_CAN1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC0
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_NFC3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_NFC3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_NFC3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_SPI2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_SPI2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SPI2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SPI2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DDR
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DDR_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DDR_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DDR_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_SDHC
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_SDHC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SDHC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_SDHC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_LCDC
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_LCDC_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_LCDC_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_LCDC_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_FTM2
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_FTM2_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM2_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM2_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_FTM3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_FTM3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_FTM3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ADC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ADC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ADC3
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ADC3_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC3_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ADC3_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_ENET
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_ENET_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ENET_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_ENET_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DAC0
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DAC0_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC0_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC0_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_DAC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_DAC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_DAC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_OSC1
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_OSC1_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_OSC1_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_OSC1_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_UART4
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_UART4_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART4_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART4_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccessGrp_UART5
+ false
+ false
+ false
+
+
+ AIPS1PrphAccess_UART5_SupervisorProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__SupervisorProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART5_WriteProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__WriteProtect
+ 1
+ disabled
+
+
+ AIPS1PrphAccess_UART5_TrustedProtect
+ false
+ false
+ false
+ typeKinetisAIPS1PrphAccess__TrustedProtect
+ 1
+ disabled
+
+
+ AIPS1InternalUsageGrp
+ false
+ false
+ true
+
+
+ AIPS1IsInitialized
+ false
+ 1
+ false
+
+
+ ShrdMCMGrp
+ 1
+
+
+ MCMGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceMCM
+ false
+ false
+
+ false
+
+
+ MCMSRAMGrp
+ false
+ false
+ false
+
+
+ MCMSRAML_Grp
+ false
+ false
+ false
+
+
+ MCMWriteProtect0
+ false
+ false
+ false
+ typeKinetisMCMWriteProtect
+ 0
+ disabled
+
+
+ MCMArbitPriority0
+ false
+ false
+ false
+ typeKinetisMCMArbitPriority
+ 0
+ roundRobin
+
+
+ MCMSRAMU_Grp
+ false
+ false
+ false
+
+
+ MCMWriteProtect1
+ false
+ false
+ false
+ typeKinetisMCMWriteProtect
+ 0
+ disabled
+
+
+ MCMArbitPriority1
+ false
+ false
+ false
+ typeKinetisMCMArbitPriority
+ 0
+ roundRobin
+
+
+ MCMETBGrp
+ false
+ false
+ false
+
+
+ MCMETB_ITM2TPIU
+ false
+ false
+ false
+ typeKinetisMCMETB_ITM2TPIU
+ 0
+ enabled
+
+
+ MCMETB_ETM2TPIU
+ false
+ false
+ false
+ typeKinetisMCMETB_ETM2TPIU
+ 0
+ enabled
+
+
+ MCMETB_ResponseType
+ false
+ false
+ false
+ typeKinetisMCMETB_ResponseType
+ 0
+ noResponse
+
+
+ MCMETB_CntRL
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ MCMETB_CntEnable
+ false
+ false
+ false
+ typeKinetisMCMETB_CntEnable
+ 1
+ disabled
+
+
+ MCMInternalUsageGrp
+ false
+ false
+ true
+
+
+ MCMIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdSCBGrp
+ 1
+
+
+ SystemControlGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceSystemControl
+ false
+ false
+
+ false
+
+
+ SystemControlSCBSettingGrp
+ false
+ false
+ false
+
+
+ SystemControlITFolding
+ false
+ false
+ false
+ typeKinetisSystemControlITFolding
+ 0
+ enabled
+
+
+ SystemControlWriteBuffer
+ false
+ false
+ false
+ typeKinetisSystemControlWriteBuffer
+ 0
+ enabled
+
+
+ SystemControlMultiCycleInstruction
+ false
+ false
+ false
+ typeKinetisSystemControlMultiCycleInstruction
+ 0
+ enabled
+
+
+ SystemControlPriorityGrouping
+ false
+ false
+ false
+ typeKinetisSystemControlPriorityGrouping
+ 4
+ 16
+
+
+ SystemControlStackAlignment
+ false
+ false
+ false
+ typeKinetisSystemControlStackAlignment
+ 0
+ 4_byte
+
+
+ SystemControlIgnoreDbusFault
+ false
+ false
+ false
+ typeKinetisSystemControlIgnoreDbusFault
+ 1
+ disabled
+
+
+ SystemControlUsageFaultGrp
+ false
+ false
+ false
+
+
+ SystemControlDivideBy0ZeroTrap
+ false
+ false
+ false
+ typeKinetisSystemControlDivideBy0ZeroTrap
+ 1
+ disabled
+
+
+ SystemControlUnalignedAccessTrap
+ false
+ false
+ false
+ typeKinetisSystemControlUnalignedAccessTrap
+ 1
+ disabled
+
+
+ SystemControlSTIRUnpriviledgedAccess
+ false
+ false
+ false
+ typeKinetisSystemControlSTIRUnpriviledgedAccess
+ 1
+ disabled
+
+
+ SystemControlInternalUsageGrp
+ false
+ false
+ true
+
+
+ SystemControlIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdPMCGrp
+ 1
+
+
+ PMCGrp
+ false
+ false
+ false
+
+
+ PeriphDevicePMC
+ false
+ false
+ PMC
+ false
+
+
+ PMCLVDreset
+ false
+ false
+ false
+ typeKinetisPMCLVDreset
+ 1
+ enabled
+
+
+ PMCLVDvoltageSelect
+ false
+ false
+ false
+ typeKinetisPMCLVDvoltageSelect
+ 0
+ low
+
+
+ PMCLVWvoltageSelect
+ false
+ false
+ false
+ typeKinetisPMCLVWvoltageSelect
+ 0
+ low
+
+
+ PMCBangapBuffer
+ false
+ false
+ false
+ typeKinetisPMCBangapBuffer
+ 0
+ disabled
+
+
+ PMCPMCIntGrp
+ false
+ false
+ true
+
+
+ PMCLVDIntName
+ INT_LVD_LVW
+
+
+ PMCLVDIntNameRequestFeatureGroup
+ false
+ false
+
+
+ PMCLVDIntNameRequest
+ false
+ false
+ false
+ typeKinetisPMCLVDIntNameRequest
+ 1
+ disabled
+
+
+ PMCLVDIntNamePriorityFeatureGroup
+ false
+ false
+
+
+ PMCLVDIntNamePriority
+ false
+ false
+ false
+ typeKinetisPMCLVDIntNamePriority
+ 0
+ 0
+
+
+ DevInit_PMCISRnameLVDGrp
+ false
+ false
+
+
+ PMCISRnameLVD
+ false
+ false
+
+ true
+
+
+ PMCLVDinterrupt
+ false
+ false
+ false
+ typeKinetisPMCLVDinterrupt
+ 1
+ disabled
+
+
+ PMCLVWinterrupt
+ false
+ false
+ false
+ typeKinetisPMCLVWinterrupt
+ 1
+ disabled
+
+
+ PMCInternalUsageGrp
+ false
+ false
+ true
+
+
+ PMCIsInitialized
+ false
+ 0
+ true
+
+
+ ShrdSCBGrp1
+ 1
+
+
+ SIMGrp
+ false
+ false
+ false
+
+
+ PeriphDeviceSIM
+ false
+ false
+ SIM
+ false
+
+
+ SIMCLKOUTGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SIMCLKOUTPin
+ false
+ false
+
+ false
+
+
+ SIMCLKOUTPinSignal
+ false
+ false
+
+
+
+ SIMCLKOUT
+ false
+ false
+ false
+ typeKinetisSIMCLKOUT
+ 0
+ flexbusClk
+
+
+ SIMCMTUARTPAD
+ false
+ false
+ false
+ typeKinetisSIMCMTUARTPAD
+ 0
+ singlePad
+
+
+ SIMSCGCGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ SIMClkGateOSC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART4
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART5
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateENET
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDAC0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDAC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateRNGA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCAN1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateNFC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDDR
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2S1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSDHC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateLCDC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateEWM
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCMT
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2C0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2C1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUART3
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSB0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCMP
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateVREF
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateLLWU
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateLPTMR0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSYSTEM_REGS
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateTSI0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTB
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTD
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTE
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePORTF
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDMA_MULTIPLEXOR0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateDMA_MULTIPLEXOR1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCAN0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateSPI1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateI2S0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateCRC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSBHS
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateUSBDCD
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePDB0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGatePIT
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFTM1
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC0
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateADC2
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateRTC
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 1
+ disabled
+
+
+ SIMClkGateFB
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateDMA
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMClkGateMPU
+ false
+ false
+ false
+ typeKinetisSIMClkGate
+ 0
+ enabled
+
+
+ SIMInternalUsageGrp
+ false
+ false
+ true
+
+
+ SIMIsInitialized
+ false
+ 0
+ true
+
+
+ Shared_CPUInterrupts
+ 1
+
+
+ CPUInterrupts
+ false
+ false
+ false
+
+
+ IntNMIGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntNMI
+ INT_NMI
+
+
+ DevInit_NMINMIInterruptISRNameGrp
+ false
+ false
+
+
+ ISRnameNMI
+ false
+ false
+
+ true
+
+
+ DevInit_Default_ISRGrp
+ false
+ false
+
+
+ DefaultISRGrp
+ false
+ false
+ true
+ false
+
+
+ IntEmpty
+
+ true
+
+
+ ISRDefaultName
+ false
+ false
+ isr_default
+ true
+
+
+ MCU_Reset_Vector_Grp
+ false
+ false
+
+
+ resetVector
+ false
+ false
+ true
+ false
+
+
+ IntVreset
+ INT_Initial_Program_Counter
+ true
+
+
+ ISRnameINITPC
+ false
+ false
+ _startup
+ true
+
+
+ IntHardFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntHardFault
+ INT_Hard_Fault
+
+
+ DevInit_InthardFaultGrp
+ false
+ false
+
+
+ ISRnameHardfault
+ false
+ false
+
+ true
+
+
+ IntMPUGrp
+ false
+ false
+ false
+
+
+ IntMPU
+ INT_UNIMPLEMENTED_A_LINE
+
+
+ DevInit_MPUGrp
+ false
+ false
+
+
+ ISRnameMPU
+ false
+ false
+
+ true
+
+
+ IntBusFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntBusFault
+ INT_Bus_Fault
+
+
+ IntBusFaultPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntBusFaultGrp
+ false
+ false
+
+
+ ISRnameBusFault
+ false
+ false
+
+ true
+
+
+ IntUsageFaultGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntUsageFault
+ INT_Usage_Fault
+
+
+ IntUsageFaultPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntUsageFaultGrp
+ false
+ false
+
+
+ ISRnameUsageFault
+ false
+ false
+
+ true
+
+
+ IntSVCallGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntSVCall
+ INT_SVCall
+
+
+ IntSVCallPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntSVCallGrp
+ false
+ false
+
+
+ ISRnameSVCall
+ false
+ false
+
+ true
+
+
+ IntPendSVGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ IntPendSV
+ INT_PendableSrvReq
+
+
+ IntPendSVPrior
+ false
+ false
+ false
+ maximal priority
+
+
+ DevInit_IntPendSVGrp
+ false
+ false
+
+
+ ISRnamePendSV
+ false
+ false
+
+ true
+
+
+ IntLossOfLockNotFeatureGrp
+ false
+ false
+
+
+ IntLossOfLockGrp
+ false
+ false
+ false
+
+
+ IntLossOfLock
+ INT_MCG
+
+
+ IntLossOfLockPrior
+ false
+ false
+ false
+ medium priority
+
+
+ MCU_Reset_Vector_Grp2
+ false
+ false
+
+
+ ISRnameLossOfLock
+ false
+ false
+
+ true
+
+
+ DDRCondGrp
+ false
+ false
+
+
+ ShrdSCBGrp2
+ 1
+
+
+ DDRGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceDDR
+ false
+ false
+
+ false
+
+
+ DDRClockGateFeatureGroup
+ false
+ false
+
+
+ DDRClockGate
+ false
+ false
+ false
+ true
+ typeKinetisDDRClockGate
+ 0
+ noInit
+
+
+ DDRBusClock
+
+
+
+ DDRLogicPHYClock
+
+
+
+ DDRDRAMClass
+ false
+ false
+ false
+ typeKinetisDDRDRAMClass
+ 0
+ DDR1
+
+
+ DDRDDRAddressSizeTranslation
+ false
+ false
+ false
+ typeKinetisDDRDDRAddressSizeTranslation
+ 0
+ DDRAddressTranslationIsDisabled
+
+
+ DDRDRAMInitGroup
+ false
+ false
+ false
+
+
+ DDRClockPulseWidth
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRegisteredDIMM
+ false
+ false
+ false
+ typeKinetisDDRRegisteredDIMM
+ 0
+ Disabled
+
+
+ DDRDelayLockedLoop
+ false
+ false
+ true
+
+
+ DDRTimeDLL
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDLLResetDelay
+ false
+ false
+ false
+ 1024
+ DEC
+
+
+ DDRDLLResetAdjustDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRNoCommand
+ false
+ false
+ false
+ typeKinetisDDRNoCommand
+ 0
+ Enabled
+
+
+ DDRResynchronizeAfterRefresh
+ false
+ false
+ false
+ typeKinetisDDRResynchronizeAfterRefresh
+ 0
+ Disabled
+
+
+ DDRTimeInitialization
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRInitializationAutoRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRModeRegistersGroup
+ false
+ false
+ true
+
+
+ DDRModeRegisterSetCommandCycleTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeMode
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRModeRegister0
+ false
+ false
+ false
+ 1024
+ HEX
+
+
+ DDRModeRegister1
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ DDRModeRegister2
+ false
+ false
+ false
+ 1024
+ HEX
+
+
+ DDRModeRegister3
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ DDROffChipDriverImpedanceAdjustmentGroup
+ false
+ false
+ true
+
+
+ DDROCDPullDownAdjustmentChipSelect
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDROCDPullUpAdjustmentChipSelect
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDROnDieTerminationGroup
+ false
+ false
+ true
+
+
+ DDRODTReadMapCS
+ false
+ false
+ false
+ typeKinetisDDRODTReadMapCS
+ 0
+ Yes
+
+
+ DDRODTWriteMapCS
+ false
+ false
+ false
+ typeKinetisDDRODTWriteMapCS
+ 0
+ Yes
+
+
+ DDRCommandsGroup
+ false
+ false
+ true
+
+
+ DDRActivateGroup
+ false
+ false
+ true
+
+
+ DDRTimeRASLockout
+ false
+ false
+ false
+ typeKinetisDDRTimeRASLockout
+ 0
+ NotSupported
+
+
+ DDRTimeRASMinimum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRowAccessMaximum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRAStoRASDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeRAStoCASDelayInterval
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRowCycleTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeFAW
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadAndWriteAccessGroup
+ false
+ false
+ true
+
+
+ DDRTimeCAStoCASDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLatencyLinear
+ false
+ false
+ false
+ typeKinetisDDRLatencyLinear
+ 0
+ Cycle_0
+
+
+ DDRLatencyGate
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatency
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteRecovery
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteToRead
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBurstModeGroup
+ false
+ false
+ true
+
+
+ DDRBurstLength
+ false
+ false
+ false
+ typeKinetisDDRBurstLength
+ 0
+ Reserved
+
+
+ DDRTimeBurstInterruptInterval
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRInterruptWriteBurst
+ false
+ false
+ false
+ typeKinetisDDRInterruptWriteBurst
+ 0
+ Disabled
+
+
+ DDRPrechargeGroup
+ false
+ false
+ true
+
+
+ DDRTimeClockEnableToPrechargeDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBankPrechargeTime
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTRPAllBank
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeReadToPrecharge
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTimeWriteRecoveryAndAutoPrecharge
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRAutoPrecharge
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRConcurrentAutoPrechargeEnable
+ false
+ false
+ false
+ typeKinetisDDRConcurrentAutoPrechargeEnable
+ 0
+ Disabled
+
+
+ DDRRefreshGroup
+ false
+ false
+ true
+
+
+ DDRTimeRefreshCommand
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRRefreshCommands
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRAutoRefreshMode
+ false
+ false
+ false
+ typeKinetisDDRAutoRefreshMode
+ 0
+ OnBurst
+
+
+ DDRTimeRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerGroup
+ false
+ false
+ true
+
+
+ DDRAutomaticEntryGroup
+ false
+ false
+ true
+
+
+ DDRLowPowerAutoMode1
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode1
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode2
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode2
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode3
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode3
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode4
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode4
+ 0
+ Disabled
+
+
+ DDRLowPowerAutoMode5
+ false
+ false
+ false
+ typeKinetisDDRLowPowerAutoMode5
+ 0
+ Disabled
+
+
+ DDRLowPowerPowerDownCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerExternalCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerIntervalCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshEnable
+ false
+ false
+ false
+ typeKinetisDDRLowPowerRefreshEnable
+ 0
+ Enabled
+
+
+ DDRSelfRefreshModesGroup
+ false
+ false
+ true
+
+
+ DDRTimeClockLowSelfRefresh
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRClockSelfRefreshEntry
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRClockSelfRefreshExit
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTXSNRParameter
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRLowPowerRefreshHold
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRAddressingGroup
+ false
+ false
+ false
+
+
+ DDRChipSelectMap
+ false
+ false
+ false
+ typeKinetisDDRChipSelectMap
+ 0
+ Disabled
+
+
+ DDREightBankMode
+ false
+ false
+ false
+ typeKinetisDDREightBankMode
+ 0
+ Banks4
+
+
+ DDRAddressPins
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRColumnSize
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDatapathWidth
+ false
+ false
+ false
+ typeKinetisDDRDatapathWidth
+ 0
+ Width16bit
+
+
+ DDRAutoPrechargeBit
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRBigEndianEnable
+ false
+ false
+ false
+ typeKinetisDDRBigEndianEnable
+ 0
+ LittleEndian
+
+
+ DDRCommandQueueGroup
+ false
+ false
+ false
+
+
+ DDRQueueFullness
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPlacementEnable
+ false
+ false
+ false
+ false
+ false
+
+
+ DDRAddressCollisionEnable
+ false
+ false
+ false
+ typeKinetisDDRAddressCollisionEnable
+ 0
+ Disabled
+
+
+ DDRBankSplitEnable
+ false
+ false
+ false
+ typeKinetisDDRBankSplitEnable
+ 0
+ Disabled
+
+
+ DDRPriorityEnable
+ false
+ false
+ false
+ typeKinetisDDRPriorityEnable
+ 0
+ Disabled
+
+
+ DDRReadWriteSameEnable
+ false
+ false
+ false
+ typeKinetisDDRReadWriteSameEnable
+ 0
+ Disabled
+
+
+ DDRSwapEnable
+ false
+ false
+ false
+ typeKinetisDDRSwapEnable
+ 0
+ Disabled
+
+
+ DDRAgeCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRCommandAgeCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPortsGroup
+ false
+ false
+ true
+
+
+ DDRWRRLatency
+ false
+ false
+ false
+ typeKinetisDDRWRRLatency
+ 0
+ FreeRunning
+
+
+ DDRWRRSharedArbitration
+ false
+ false
+ false
+ typeKinetisDDRWRRSharedArbitration
+ 0
+ Independent
+
+
+ DDRPort0Group
+ false
+ false
+ false
+
+
+ DDRPort0Order
+ false
+ false
+ false
+ typeKinetisDDRPort0Order
+ 0
+ Highest
+
+
+ DDRPort0Type
+ false
+ false
+ false
+ typeKinetisDDRPort0Type
+ 0
+ Asynchronous
+
+
+ DDRPort0ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort0ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort0WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort0WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort0PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort0RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort0Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort0Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort0Priority3Commands
+ 0
+ Lowest
+
+
+ DDRPort1Group
+ false
+ false
+ false
+
+
+ DDRPort1Order
+ false
+ false
+ false
+ typeKinetisDDRPort1Order
+ 0
+ Highest
+
+
+ DDRPort1Type
+ false
+ false
+ false
+ typeKinetisDDRPort1Type
+ 0
+ Asynchronous
+
+
+ DDRPort1ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort1ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort1WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort1WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort1PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort1RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort1Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort1Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort1Priority3Commands
+ 0
+ Lowest
+
+
+ DDRPort2Group
+ false
+ false
+ false
+
+
+ DDRPort2Order
+ false
+ false
+ false
+ typeKinetisDDRPort2Order
+ 0
+ Highest
+
+
+ DDRPort2Type
+ false
+ false
+ false
+ typeKinetisDDRPort2Type
+ 0
+ Asynchronous
+
+
+ DDRPort2ReadCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2WriteCount
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2ReadCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort2ReadCommandPriority
+ 0
+ Highest
+
+
+ DDRPort2WriteCommandPriority
+ false
+ false
+ false
+ typeKinetisDDRPort2WriteCommandPriority
+ 0
+ Highest
+
+
+ DDRPort2PriorityRelax
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRPort2RelativePriorities
+ false
+ false
+ true
+
+
+ DDRPort2Priority0Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority0Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority1Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority1Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority2Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority2Commands
+ 0
+ Lowest
+
+
+ DDRPort2Priority3Commands
+ false
+ false
+ false
+ typeKinetisDDRPort2Priority3Commands
+ 0
+ Lowest
+
+
+ DDRFastWrite
+ false
+ false
+ false
+ typeKinetisDDRFastWrite
+ 0
+ Disabled
+
+
+ DDRAdditionalDelaysGroup
+ false
+ false
+ true
+
+
+ DDRR2RSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRR2WSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRW2RSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRW2WSameChipSelectDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYGroup
+ false
+ false
+ false
+
+
+ DDRCommandDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRCommandLatencyReductionEnable
+ false
+ false
+ false
+ typeKinetisDDRCommandLatencyReductionEnable
+ 0
+ Disabled
+
+
+ DDRWriteGroup
+ false
+ false
+ true
+
+
+ DDRPHYWriteLatencyBase
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatencyAdjust
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRWriteLatencyReductionEnable
+ false
+ false
+ false
+ typeKinetisDDRWriteLatencyReductionEnable
+ 0
+ Disabled
+
+
+ DDRReadGroup
+ false
+ false
+ true
+
+
+ DDRPHYReadLatency
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadLatencyAdjust
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRReadDataEnableBase
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRUpdateGroup
+ false
+ false
+ true
+
+
+ DDRDFICTRLUPDMinimum
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType0
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType1
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType2
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIPHYUPDType3
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRTDFIPHYUPDRESPParameter
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDRAMClockGroup
+ false
+ false
+ true
+
+
+ DDRDFIClockDisableDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRDFIClockEnableDelay
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ DDRODTAlternateEnable
+ false
+ false
+ false
+ typeKinetisDDRODTAlternateEnable
+ 0
+ Disabled
+
+
+ DDRPinsGroup
+ false
+ false
+ false
+
+
+ DDRPinEnableForAllDDRIO
+ false
+ false
+ false
+ typeKinetisDDRPinEnableForAllDDRIO
+ 0
+ disabled
+
+
+ DDRDDRConfigurationSelect
+ false
+ false
+ false
+ typeKinetisDDRDDRConfigurationSelect
+ 0
+ LPDDRHalfStrength
+
+
+ DDRDDRSelfRefreshEnable
+ false
+ false
+ false
+ typeKinetisDDRDDRSelfRefreshEnable
+ 0
+ disabled
+
+
+ DDRSpareDelayCtrl
+ false
+ false
+ false
+ typeKinetisDDRSpareDelayCtrl
+ 0
+ NoBuffer
+
+
+ DDRODTResistor
+ false
+ false
+ false
+ typeKinetisDDRODTResistor
+ 0
+ ODTDisabled
+
+
+ DDRPin0Group
+ false
+ false
+ false
+
+
+ DDRPin0
+ false
+ false
+
+ false
+
+
+ DDRPin0Signal
+ false
+ false
+
+
+
+ DDRPin1Group
+ false
+ false
+ false
+
+
+ DDRPin1
+ false
+ false
+
+ false
+
+
+ DDRPin1Signal
+ false
+ false
+
+
+
+ DDRPin2Group
+ false
+ false
+ false
+
+
+ DDRPin2
+ false
+ false
+
+ false
+
+
+ DDRPin2Signal
+ false
+ false
+
+
+
+ DDRPin3Group
+ false
+ false
+ false
+
+
+ DDRPin3
+ false
+ false
+
+ false
+
+
+ DDRPin3Signal
+ false
+ false
+
+
+
+ DDRPin4Group
+ false
+ false
+ false
+
+
+ DDRPin4
+ false
+ false
+
+ false
+
+
+ DDRPin4Signal
+ false
+ false
+
+
+
+ DDRPin5Group
+ false
+ false
+ false
+
+
+ DDRPin5
+ false
+ false
+
+ false
+
+
+ DDRPin5Signal
+ false
+ false
+
+
+
+ DDRPin6Group
+ false
+ false
+ false
+
+
+ DDRPin6
+ false
+ false
+
+ false
+
+
+ DDRPin6Signal
+ false
+ false
+
+
+
+ DDRPin7Group
+ false
+ false
+ false
+
+
+ DDRPin7
+ false
+ false
+
+ false
+
+
+ DDRPin7Signal
+ false
+ false
+
+
+
+ DDRPin8Group
+ false
+ false
+ false
+
+
+ DDRPin8
+ false
+ false
+
+ false
+
+
+ DDRPin8Signal
+ false
+ false
+
+
+
+ DDRPin9Group
+ false
+ false
+ false
+
+
+ DDRPin9
+ false
+ false
+
+ false
+
+
+ DDRPin9Signal
+ false
+ false
+
+
+
+ DDRPin10Group
+ false
+ false
+ false
+
+
+ DDRPin10
+ false
+ false
+
+ false
+
+
+ DDRPin10Signal
+ false
+ false
+
+
+
+ DDRPin11Group
+ false
+ false
+ false
+
+
+ DDRPin11
+ false
+ false
+
+ false
+
+
+ DDRPin11Signal
+ false
+ false
+
+
+
+ DDRPin12Group
+ false
+ false
+ false
+
+
+ DDRPin12
+ false
+ false
+
+ false
+
+
+ DDRPin12Signal
+ false
+ false
+
+
+
+ DDRPin13Group
+ false
+ false
+ false
+
+
+ DDRPin13
+ false
+ false
+
+ false
+
+
+ DDRPin13Signal
+ false
+ false
+
+
+
+ DDRPin14Group
+ false
+ false
+ false
+
+
+ DDRPin14
+ false
+ false
+
+ false
+
+
+ DDRPin14Signal
+ false
+ false
+
+
+
+ DDRPin15Group
+ false
+ false
+ false
+
+
+ DDRPin15
+ false
+ false
+
+ false
+
+
+ DDRPin15Signal
+ false
+ false
+
+
+
+ DDRPin16Group
+ false
+ false
+ false
+
+
+ DDRPin16
+ false
+ false
+
+ false
+
+
+ DDRPin16Signal
+ false
+ false
+
+
+
+ DDRPin17Group
+ false
+ false
+ false
+
+
+ DDRPin17
+ false
+ false
+
+ false
+
+
+ DDRPin17Signal
+ false
+ false
+
+
+
+ DDRPin19Group
+ false
+ false
+ false
+
+
+ DDRPin19
+ false
+ false
+
+ false
+
+
+ DDRPin19Signal
+ false
+ false
+
+
+
+ DDRPin20Group
+ false
+ false
+ false
+
+
+ DDRPin20
+ false
+ false
+
+ false
+
+
+ DDRPin20Signal
+ false
+ false
+
+
+
+ DDRPin21Group
+ false
+ false
+ false
+
+
+ DDRPin21
+ false
+ false
+
+ false
+
+
+ DDRPin21Signal
+ false
+ false
+
+
+
+ DDRPin23Group
+ false
+ false
+ false
+
+
+ DDRPin23
+ false
+ false
+
+ false
+
+
+ DDRPin23Signal
+ false
+ false
+
+
+
+ DDRPin24Group
+ false
+ false
+ false
+
+
+ DDRPin24
+ false
+ false
+
+ false
+
+
+ DDRPin24Signal
+ false
+ false
+
+
+
+ DDRPin25Group
+ false
+ false
+ false
+
+
+ DDRPin25
+ false
+ false
+
+ false
+
+
+ DDRPin25Signal
+ false
+ false
+
+
+
+ DDRPin26Group
+ false
+ false
+ false
+
+
+ DDRPin26
+ false
+ false
+
+ false
+
+
+ DDRPin26Signal
+ false
+ false
+
+
+
+ DDRPin27Group
+ false
+ false
+ false
+
+
+ DDRPin27
+ false
+ false
+
+ false
+
+
+ DDRPin27Signal
+ false
+ false
+
+
+
+ DDRPin28Group
+ false
+ false
+ false
+
+
+ DDRPin28
+ false
+ false
+
+ false
+
+
+ DDRPin28Signal
+ false
+ false
+
+
+
+ DDRPin29Group
+ false
+ false
+ false
+
+
+ DDRPin29
+ false
+ false
+
+ false
+
+
+ DDRPin29Signal
+ false
+ false
+
+
+
+ DDRPin30Group
+ false
+ false
+ false
+
+
+ DDRPin30
+ false
+ false
+
+ false
+
+
+ DDRPin30Signal
+ false
+ false
+
+
+
+ DDRPin31Group
+ false
+ false
+ false
+
+
+ DDRPin31
+ false
+ false
+
+ false
+
+
+ DDRPin31Signal
+ false
+ false
+
+
+
+ DDRPin32Group
+ false
+ false
+ false
+
+
+ DDRPin32
+ false
+ false
+
+ false
+
+
+ DDRPin32Signal
+ false
+ false
+
+
+
+ DDRPin33Group
+ false
+ false
+ false
+
+
+ DDRPin33
+ false
+ false
+
+ false
+
+
+ DDRPin33Signal
+ false
+ false
+
+
+
+ DDRPin34Group
+ false
+ false
+ false
+
+
+ DDRPin34
+ false
+ false
+
+ false
+
+
+ DDRPin34Signal
+ false
+ false
+
+
+
+ DDRPin35Group
+ false
+ false
+ false
+
+
+ DDRPin35
+ false
+ false
+
+ false
+
+
+ DDRPin35Signal
+ false
+ false
+
+
+
+ DDRPin36Group
+ false
+ false
+ false
+
+
+ DDRPin36
+ false
+ false
+
+ false
+
+
+ DDRPin36Signal
+ false
+ false
+
+
+
+ DDRPin37Group
+ false
+ false
+ false
+
+
+ DDRPin37
+ false
+ false
+
+ false
+
+
+ DDRPin37Signal
+ false
+ false
+
+
+
+ DDRPin38Group
+ false
+ false
+ false
+
+
+ DDRPin38
+ false
+ false
+
+ false
+
+
+ DDRPin38Signal
+ false
+ false
+
+
+
+ DDRPin39Group
+ false
+ false
+ false
+
+
+ DDRPin39
+ false
+ false
+
+ false
+
+
+ DDRPin39Signal
+ false
+ false
+
+
+
+ DDRPin40Group
+ false
+ false
+ false
+
+
+ DDRPin40
+ false
+ false
+
+ false
+
+
+ DDRPin40Signal
+ false
+ false
+
+
+
+ DDRPin41Group
+ false
+ false
+ false
+
+
+ DDRPin41
+ false
+ false
+
+ false
+
+
+ DDRPin41Signal
+ false
+ false
+
+
+
+ DDRPin42Group
+ false
+ false
+ false
+
+
+ DDRPin42
+ false
+ false
+
+ false
+
+
+ DDRPin42Signal
+ false
+ false
+
+
+
+ DDRPin43Group
+ false
+ false
+ false
+
+
+ DDRPin43
+ false
+ false
+
+ false
+
+
+ DDRPin43Signal
+ false
+ false
+
+
+
+ DDRPin46Group
+ false
+ false
+ false
+
+
+ DDRPin46
+ false
+ false
+
+ false
+
+
+ DDRPin46Signal
+ false
+ false
+
+
+
+ DDRPin47Group
+ false
+ false
+ false
+
+
+ DDRPin47
+ false
+ false
+
+ false
+
+
+ DDRPin47Signal
+ false
+ false
+
+
+
+ DDRPin48Group
+ false
+ false
+ false
+
+
+ DDRPin48
+ false
+ false
+
+ false
+
+
+ DDRPin48Signal
+ false
+ false
+
+
+
+ DDRPin49Group
+ false
+ false
+ false
+
+
+ DDRPin49
+ false
+ false
+
+ false
+
+
+ DDRPin49Signal
+ false
+ false
+
+
+
+ DDRPin50Group
+ false
+ false
+ false
+
+
+ DDRPin50
+ false
+ false
+
+ false
+
+
+ DDRPin50Signal
+ false
+ false
+
+
+
+ DDRPin51Group
+ false
+ false
+ false
+
+
+ DDRPin51
+ false
+ false
+
+ false
+
+
+ DDRPin51Signal
+ false
+ false
+
+
+
+ DDRPin52Group
+ false
+ false
+ false
+
+
+ DDRPin52
+ false
+ false
+
+ false
+
+
+ DDRPin52Signal
+ false
+ false
+
+
+
+ DDRPin53Group
+ false
+ false
+ false
+
+
+ DDRPin53
+ false
+ false
+
+ false
+
+
+ DDRPin53Signal
+ false
+ false
+
+
+
+ DDRPin54Group
+ false
+ false
+ false
+
+
+ DDRPin54
+ false
+ false
+
+ false
+
+
+ DDRPin54Signal
+ false
+ false
+
+
+
+ DDRPin55Group
+ false
+ false
+ false
+
+
+ DDRPin55
+ false
+ false
+
+ false
+
+
+ DDRPin55Signal
+ false
+ false
+
+
+
+ DDRPin56Group
+ false
+ false
+ false
+
+
+ DDRPin56
+ false
+ false
+
+ false
+
+
+ DDRPin56Signal
+ false
+ false
+
+
+
+ DDRPin57Group
+ false
+ false
+ false
+
+
+ DDRPin57
+ false
+ false
+
+ false
+
+
+ DDRPin57Signal
+ false
+ false
+
+
+
+ DDRPin58Group
+ false
+ false
+ false
+
+
+ DDRPin58
+ false
+ false
+
+ false
+
+
+ DDRPin58Signal
+ false
+ false
+
+
+
+ DDRPin59Group
+ false
+ false
+ false
+
+
+ DDRPin59
+ false
+ false
+
+ false
+
+
+ DDRPin59Signal
+ false
+ false
+
+
+
+ DDRPin60Group
+ false
+ false
+ false
+
+
+ DDRPin60
+ false
+ false
+
+ false
+
+
+ DDRPin60Signal
+ false
+ false
+
+
+
+ DDRPin61Group
+ false
+ false
+ false
+
+
+ DDRPin61
+ false
+ false
+
+ false
+
+
+ DDRPin61Signal
+ false
+ false
+
+
+
+ DDRPin62Group
+ false
+ false
+ false
+
+
+ DDRPin62
+ false
+ false
+
+ false
+
+
+ DDRPin62Signal
+ false
+ false
+
+
+
+ DDRPin63Group
+ false
+ false
+ false
+
+
+ DDRPin63
+ false
+ false
+
+ false
+
+
+ DDRPin63Signal
+ false
+ false
+
+
+
+ DDRPin64Group
+ false
+ false
+ false
+
+
+ DDRPin64
+ false
+ false
+
+ false
+
+
+ DDRPin64Signal
+ false
+ false
+
+
+
+ DDRPin65Group
+ false
+ false
+ false
+
+
+ DDRPin65
+ false
+ false
+
+ false
+
+
+ DDRPin65Signal
+ false
+ false
+
+
+
+ DDRPin66Group
+ false
+ false
+ false
+
+
+ DDRPin66
+ false
+ false
+
+ false
+
+
+ DDRPin66Signal
+ false
+ false
+
+
+
+ DDRPin73Group
+ false
+ false
+ false
+
+
+ DDRPin73
+ false
+ false
+
+ false
+
+
+ DDRPin73Signal
+ false
+ false
+
+
+
+ DDRPin74Group
+ false
+ false
+ false
+
+
+ DDRPin74
+ false
+ false
+
+ false
+
+
+ DDRPin74Signal
+ false
+ false
+
+
+
+ DDRPin75Group
+ false
+ false
+ false
+
+
+ DDRPin75
+ false
+ false
+
+ false
+
+
+ DDRPin75Signal
+ false
+ false
+
+
+
+ DDRInterruptsGroup
+ false
+ false
+ false
+
+
+ DDRInterrupt
+
+
+
+ DDRInterruptRequestFeatureGroup
+ false
+ false
+
+
+ DDRInterruptRequest
+ false
+ false
+ false
+ true
+ typeKinetisDDRInterruptRequest
+ 1
+ disabled
+
+
+ DDRInterruptPriorityFeatureGroup
+ false
+ false
+
+
+ DDRInterruptPriority
+ false
+ false
+ false
+ true
+ typeKinetisDDRInterruptPriority
+ 0
+ 0
+
+
+ DevInit_DDRISRHandleNameGrp
+ false
+ false
+
+
+ DDRISRHandleName
+ false
+ false
+
+ true
+
+
+ DDRInterruptAnyFlagEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptAnyFlagEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDLLResyncFinishedEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDLLResyncFinishedEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDFICompleteEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDFICompleteEnable
+ 0
+ Disabled
+
+
+ DDRInterruptWriteFinishedEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptWriteFinishedEnable
+ 0
+ Disabled
+
+
+ DDRInterruptODTConfigErrorEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptODTConfigErrorEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDDR2MobileEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDDR2MobileEnable
+ 0
+ Disabled
+
+
+ DDRInterruptDRAMInitCompleteEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptDRAMInitCompleteEnable
+ 0
+ Disabled
+
+
+ DDRInterruptMultipleOutOfRangeEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptMultipleOutOfRangeEnable
+ 0
+ Disabled
+
+
+ DDRInterruptSingleOutOfRangeEnable
+ false
+ false
+ false
+ typeKinetisDDRInterruptSingleOutOfRangeEnable
+ 0
+ Disabled
+
+
+ DDRInternalUsageGrp
+ false
+ false
+ true
+
+
+ DDRIsInitialized
+ false
+ 1
+ false
+
+
+ ShrdFBusGrp
+ 1
+
+
+ ExternalBusGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceExternalBus
+ false
+ false
+
+ false
+
+
+ ExternalBusFBSecurity
+ false
+ false
+ false
+ typeKinetisExternalBusFBSecurity
+ 0
+ AllDisallowed
+
+
+ ExternalBusChipSelectsGrp
+ false
+ false
+ true
+
+
+ ExternalBusCS0
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS0BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS0BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize0
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced0
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS0WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS0WaitStates
+ false
+ false
+ false
+ 63
+ DEC
+
+
+ ExternalBusCS0SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS0SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS0ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS0AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 3
+ 11
+
+
+ ExternalBusCS0ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 3
+ 11
+
+
+ ExternalBusCS0WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 3
+ 11
+
+
+ ExternalBusCS0BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS0AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS0PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS0ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS0BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS0BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS0PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS1
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS1BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS1BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize1
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced1
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS1WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS1WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS1SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS1SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS1ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS1AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS1ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS1WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS1BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS1AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS1PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS1ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS1BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS1BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS1PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS2
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS2BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS2BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize2
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced2
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS2WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS2WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS2SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS2SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS2ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS2AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS2ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS2WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS2BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS2AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS2PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS2ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS2BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS2BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS2PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS3
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS3BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS3BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize3
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced3
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS3WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS3WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS3SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS3SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS3ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS3AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS3ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS3WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS3BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS3AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS3PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS3ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS3BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS3BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS3PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS4
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS4BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS4BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize4
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced4
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS4WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS4WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS4SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS4SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS4ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS4AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS4ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS4WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS4BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS4AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS4PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS4ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS4BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS4BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS4PinSignal
+ false
+ false
+
+
+
+ ExternalBusCS5
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS5BaseAddr
+ false
+ false
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS5BaseAddrMask
+ false
+ false
+ false
+ 65535
+ HEX
+
+
+ ExternalBusBlockSize5
+ false
+ 0
+ HEX
+
+
+ ExternalBusBlockMaskReduced5
+ false
+ 0
+ HEX
+
+
+ ExternalBusCS5WriteProtect
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteProtect
+ 0
+ disabled
+
+
+ ExternalBusCS5WaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS5SecWaitStates
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusCS5SecondaryWaitStates
+ false
+ false
+ false
+ 0
+ DEC
+
+
+ ExternalBusCS5ExtendedTransfer
+ false
+ false
+ false
+ typeKinetisExternalBusCSExtendedTransfer
+ 0
+ disabled
+
+
+ ExternalBusCS5AddressSetup
+ false
+ false
+ false
+ typeKinetisExternalBusCSAddressSetup
+ 0
+ 00
+
+
+ ExternalBusCS5ReadAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSReadAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS5WriteAddrHold
+ false
+ false
+ false
+ typeKinetisExternalBusCSWriteAddrHold
+ 0
+ 00
+
+
+ ExternalBusCS5BLSMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSBLSMode
+ 0
+ leftJustified
+
+
+ ExternalBusCS5AutoAcknowledge
+ false
+ false
+ false
+ typeKinetisExternalBusCSAutoAcknowledge
+ 1
+ enabled
+
+
+ ExternalBusCS5PortSize
+ false
+ false
+ false
+ typeKinetisExternalBusCSPortSize
+ 1
+ 01
+
+
+ ExternalBusCS5ByteMode
+ false
+ false
+ false
+ typeKinetisExternalBusCSByteMode
+ 0
+ disabled
+
+
+ ExternalBusCS5BurstRead
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstRead
+ 0
+ disabled
+
+
+ ExternalBusCS5BurstWrite
+ false
+ false
+ false
+ typeKinetisExternalBusCSBurstWrite
+ 0
+ disabled
+
+
+ ExternalBusCS5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusCS5PinSignal
+ false
+ false
+
+
+
+ ExternalBusAddrPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusA16PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr16Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr16PinSignal
+ false
+ false
+
+
+
+ ExternalBusA17PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr17PinSignal
+ false
+ false
+
+
+
+ ExternalBusA18PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr18PinSignal
+ false
+ false
+
+
+
+ ExternalBusA19PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr19Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr19PinSignal
+ false
+ false
+
+
+
+ ExternalBusA20PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr20Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr20PinSignal
+ false
+ false
+
+
+
+ ExternalBusA21PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr21Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr21PinSignal
+ false
+ false
+
+
+
+ ExternalBusA22PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr22Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr22PinSignal
+ false
+ false
+
+
+
+ ExternalBusA23PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr23Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr23PinSignal
+ false
+ false
+
+
+
+ ExternalBusA24PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr24Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr24PinSignal
+ false
+ false
+
+
+
+ ExternalBusA25PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr25Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr25PinSignal
+ false
+ false
+
+
+
+ ExternalBusA26PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr26Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr26PinSignal
+ false
+ false
+
+
+
+ ExternalBusA27PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr27Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr27PinSignal
+ false
+ false
+
+
+
+ ExternalBusA28PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr28Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr28PinSignal
+ false
+ false
+
+
+
+ ExternalBusA29PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusAddr29Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusAddr29PinSignal
+ false
+ false
+
+
+
+ ExternalBusDataPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusD0PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData0PinSignal
+ false
+ false
+
+
+
+ ExternalBusD1PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData1PinSignal
+ false
+ false
+
+
+
+ ExternalBusD2PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData2PinSignal
+ false
+ false
+
+
+
+ ExternalBusD3PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData3PinSignal
+ false
+ false
+
+
+
+ ExternalBusD4PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData4PinSignal
+ false
+ false
+
+
+
+ ExternalBusD5PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData5PinSignal
+ false
+ false
+
+
+
+ ExternalBusD6PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData6Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData6PinSignal
+ false
+ false
+
+
+
+ ExternalBusD7PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData7Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData7PinSignal
+ false
+ false
+
+
+
+ ExternalBusD8PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData8Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData8PinSignal
+ false
+ false
+
+
+
+ ExternalBusD9PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData9Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData9PinSignal
+ false
+ false
+
+
+
+ ExternalBusD10PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData10Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData10PinSignal
+ false
+ false
+
+
+
+ ExternalBusD11PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData11Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData11PinSignal
+ false
+ false
+
+
+
+ ExternalBusD12PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData12Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData12PinSignal
+ false
+ false
+
+
+
+ ExternalBusD13PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData13Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData13PinSignal
+ false
+ false
+
+
+
+ ExternalBusD14PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData14Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData14PinSignal
+ false
+ false
+
+
+
+ ExternalBusD15PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData15Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData15PinSignal
+ false
+ false
+
+
+
+ ExternalBusD16PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData16Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData16PinSignal
+ false
+ false
+
+
+
+ ExternalBusD17PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData17PinSignal
+ false
+ false
+
+
+
+ ExternalBusD18PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData18PinSignal
+ false
+ false
+
+
+
+ ExternalBusD19PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData19Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData19PinSignal
+ false
+ false
+
+
+
+ ExternalBusD20PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData20Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData20PinSignal
+ false
+ false
+
+
+
+ ExternalBusD21PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData21Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData21PinSignal
+ false
+ false
+
+
+
+ ExternalBusD22PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData22Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData22PinSignal
+ false
+ false
+
+
+
+ ExternalBusD23PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData23Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData23PinSignal
+ false
+ false
+
+
+
+ ExternalBusD24PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData24Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData24PinSignal
+ false
+ false
+
+
+
+ ExternalBusD25PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData25Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData25PinSignal
+ false
+ false
+
+
+
+ ExternalBusD26PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData26Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData26PinSignal
+ false
+ false
+
+
+
+ ExternalBusD27PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData27Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData27PinSignal
+ false
+ false
+
+
+
+ ExternalBusD28PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData28Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData28PinSignal
+ false
+ false
+
+
+
+ ExternalBusD29PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData29Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData29PinSignal
+ false
+ false
+
+
+
+ ExternalBusD30PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData30Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData30PinSignal
+ false
+ false
+
+
+
+ ExternalBusD31PinGrp
+ false
+ false
+ false
+ true
+ true
+
+
+ ExternalBusData31Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusData31PinSignal
+ false
+ false
+
+
+
+ ExternalBusControlPinsGroup
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl0PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl0Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl0PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl1PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl1Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl1PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl2PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl2Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl2PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl3PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl3Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl3PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl4PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl4Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl4PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl5PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl5Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl5PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl6PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl6Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl6PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl7PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl7Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl7PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl13PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl13Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl13PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl14PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl14Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl14PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl17PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl17Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl17PinSignal
+ false
+ false
+
+
+
+ ExternalBusControl18PinGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ ExternalBusControl18Pin
+ false
+ false
+
+ false
+
+
+ ExternalBusControl18PinSignal
+ false
+ false
+
+
+
+ _ExtMemGrp
+ false
+ 0
+ false
+ true
+
+
+ ExternalBusInternalUsageGrp
+ false
+ false
+ true
+
+
+ ExternalBusIsInitialized
+ false
+ 1
+ false
+
+
+ LowPowerModesGrp
+ false
+ false
+ false
+
+
+ Shared_CPULowPowerGrp
+ 1
+
+
+ AllowedPowerModesGrp
+ false
+ false
+ false
+
+
+ SMC_AHSRUNCondGrp
+ false
+ false
+
+
+ SMC_AHSRUN
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ SMC_AVLP
+ false
+ false
+ false
+ 0
+ true
+
+
+ SMC_ALLS
+ false
+ false
+ false
+ 0
+ true
+
+
+ SMC_AVLLS
+ false
+ false
+ false
+ 0
+ true
+
+
+ ShrdLLWUGrp
+ 1
+
+
+ LLWUGrp
+ false
+ false
+ false
+ false
+ false
+
+
+ PeriphDeviceLLWU
+ false
+ false
+
+ false
+
+
+ LLWULLWUSettingGrp
+ false
+ false
+ false
+
+
+ LLWUExtPin0
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan0Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin1
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan1Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin2
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan2Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin3
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan3Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin4
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan4Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin5
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan5Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin6
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan6Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin7
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan7Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin8
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan8Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin9
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan9Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin10
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan10Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin11
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan11Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin12
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan12Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin13
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan13Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin14
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan14Signal
+ false
+ false
+
+ true
+
+
+ LLWUExtPin15
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUExtPinChan15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUExtPinChan15Signal
+ false
+ false
+
+ true
+
+
+ LLWUIntModule0
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule1
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule2
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule3
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule4
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule5
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUIntModule7
+ false
+ false
+ false
+ typeKinetisLLWUIntModule
+ 0
+ disabled
+
+
+ LLWUFiltr1
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUFilt1In
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ LLWUFilt1ExtPin0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin0Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin1Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin2Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin3Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin4Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin5Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin6Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin7Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin8Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin9Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin10Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin11Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin12Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin13Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin14Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt1ExtPin15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt1ExtPin15Signal
+ false
+ false
+
+ true
+
+
+ LLWUFiltr2
+ false
+ false
+ false
+ 0
+ true
+
+
+ LLWUFilt2In
+ false
+ false
+ false
+ true
+ 0
+ true
+
+
+ LLWUFilt2ExtPin0
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin0Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin1
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin1Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin2
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin2Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin3
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin3Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin4
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin4Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin5
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin5Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin6
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin6Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin7
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin7Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin8
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin8Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin9
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin9Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin10
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin10Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin11
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin11Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin12
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin12Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin13
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin13Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin14
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin14Signal
+ false
+ false
+
+ true
+
+
+ LLWUFilt2ExtPin15
+ false
+ false
+
+ true
+ false
+
+
+ LLWUFilt2ExtPin15Signal
+ false
+ false
+
+ true
+
+
+ LLWUReset
+ false
+ false
+ false
+ true
+ true
+
+
+ LLWUResetPinFilter
+ false
+ false
+ false
+ typeKinetisLLWUResetPinFilter
+ 0
+ disabled
+
+
+ LLWUInterruptsGroup
+ false
+ false
+ false
+
+
+ LLWUIntCommon
+
+
+
+ LLWUIntCommonRequestFeatureGroup
+ false
+ false
+
+
+ LLWUIntCommonRequest
+ false
+ false
+ false
+ true
+ typeKinetisLLWUIntCommonRequest
+ 1
+ disabled
+
+
+ LLWUIntCommonPriorityFeatureGroup
+ false
+ false
+
+
+ LLWUIntCommonPriority
+ false
+ false
+ false
+ true
+ typeKinetisLLWUIntCommonPriority
+ 0
+ 0
+
+
+ DevInit_LLWUISRHandleCommonGrp
+ false
+ false
+
+
+ LLWUISRHandleCommon
+ false
+ false
+
+ true
+
+
+ LLWUInternalUsageGrp
+ false
+ false
+ true
+
+
+ LLWUIsInitialized
+ false
+ 1
+ false
+
+
+ Shared_CPULowPowerGrp0
+ 1
+
+
+ SetLowPowerModeGrp
+ false
+ false
+
+
+ SetOperationModeGrp
+ false
+ false
+ false
+
+
+ SetOperationMode_WAIT
+ false
+ false
+ false
+
+
+ SetOperationMode_WAIT_SLEEPONEXIT
+ false
+ false
+ false
+ 1
+ false
+
+
+ SetOperationMode_SLEEP
+ false
+ false
+ false
+
+
+ SetOperationMode_SLEEP_SLEEPONEXIT
+ false
+ false
+ false
+ 1
+ false
+
+
+ SetOperationMode_STOP
+ false
+ false
+ false
+ false
+ false
+
+
+ SetOperationMode_STOP_Sel
+ false
+ false
+ false
+ 0
+ 0
+
+
+ SpeedModeList
+ false
+ 1
+ false
+ true
+
+
+ SpeedMode0
+ false
+ false
+ true
+
+
+ ClkSrcSettingsGrpSpeedMode0
+ false
+ false
+ false
+
+
+ IRC_32kHzSpeedMode0
+ false
+ false
+ false
+ 0.032768
+
+
+ IRC_4MHzSpeedMode0
+ false
+ 2
+
+
+ SYSTEM_OSCSpeedMode0
+ false
+ false
+ false
+ 8
+
+
+ OSC1CLKSpeedMode0
+ false
+ false
+ false
+ 8
+
+
+ RTC_OSCSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ _SYSTEM_PRESCALER0
+ false
+ false
+ false
+
+
+ IRCLKSelSpeedMode0
+ false
+ false
+ false
+ IRC_32kHz
+
+
+ MCG_ERCLKSelSpeedMode0
+ false
+ false
+ false
+ SYSTEM_OSC
+
+
+ PLLREFSEL0SelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ PLLREFSEL1SelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ ERCLK32KSelSpeedMode0
+ false
+ false
+ false
+ SYSTEM_OSC
+
+
+ MCG_FLL_RCLKSelSpeedMode0
+ false
+ false
+ false
+ IRC_32kHz
+
+
+ MCG_FRDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_FLL_MFactorSpeedMode0
+ false
+ false
+ false
+ 640
+
+
+ MCG_PRDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_VDIVSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_PRDIV1SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCG_VDIV1SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCGPLLCSCLKSelSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ MCGOUTSelSpeedMode0
+ false
+ false
+ false
+ MCGFLLCLK
+
+
+ VLPRSpeedMode0
+ false
+ false
+ false
+ false
+ false
+
+
+ VLPREntrySpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ VLPExitOnIntSpeedMode0
+ false
+ false
+ false
+ 1
+ false
+
+
+ CLKModeSpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ MCGModeSelSpeedMode0
+ false
+ 0
+ 0
+
+
+ MCGOutputSpeedMode0
+ false
+ 20.97152
+
+
+ IRCLKClkSpeedMode0
+ 0.032768
+
+
+ ERCLKClkSpeedMode0
+ 0
+
+
+ ERCLK32KClkSpeedMode0
+ 0
+
+
+ FLLFixedClkSpeedMode0
+ 16.384
+
+
+ SystemClocksGrp0
+ false
+ false
+ true
+
+
+ OUTDIV1PrescSpeedMode0
+ false
+ false
+ false
+ 1
+
+
+ OUTDIV1Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ CoreClockSpeedMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ OUTDIV2PrescSpeedMode0
+ false
+ false
+ false
+ 1
+
+
+ OUTDIV2Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ BusClockSpeedMode0
+ false
+ false
+ false
+ 20.97152
+
+
+ OUTDIV3PrescSpeedMode0
+ false
+ false
+ false
+ 2
+
+
+ OUTDIV3Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ ExternalBusClockSpeedMode0
+ false
+ false
+ false
+ 10.48576
+
+
+ OUTDIV4PrescSpeedMode0
+ false
+ false
+ false
+ 2
+
+
+ OUTDIV4Presc_SpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ FlashClockSpeedMode0
+ false
+ false
+ false
+ 10.48576
+
+
+ USB0_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ USBHS_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ PLLFLLCLkSelSpeedMode0
+ false
+ false
+ false
+ 0
+ true
+
+
+ PLLFLLSelSpeedMode0
+ false
+ false
+ false
+ MCGFLLCLK
+
+
+ PLLFLLClockSpeedMode0
+ false
+ 20.97152
+
+
+ I2S0_CLKINCondGrp0
+ false
+ false
+
+
+ I2S0_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ I2S1_CLKINCondGrp0
+ false
+ false
+
+
+ I2S1_CLKINSpeedMode0
+ false
+ false
+ false
+ 0
+
+
+ I2SClockCondGrp0
+ false
+ false
+
+
+ I2SClockGrp0
+ false
+ false
+ true
+
+
+ I2S0_MclkClkSrcCondGrp0
+ false
+ false
+
+
+ I2S0_MclkPinSourceSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+ I2S1_MclkClkSrcCondGrp0
+ false
+ false
+
+
+ I2S1_MclkPinSourceSpeedMode0
+ false
+ false
+ false
+ Auto select
+
+
+
+
+ CPUCond
+ 1
+
+
+ SharedCpuMethodsInvisibleGroup
+ false
+ false
+
+
+ SetClockConfiguration
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SetClockConfiguration
+
+
+ GetClockConfiguration
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ GetClockConfiguration
+
+
+ SetOperationMode
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SetOperationMode
+
+
+ EnableInt
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ EnableInt
+
+
+ DisableInt
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ DisableInt
+
+
+ GetLLSWakeUpFlagsPDD2CondGrp
+ false
+ false
+
+
+ GetLLSWakeUpFlagsCondGrp
+ false
+ false
+
+
+ GetLLSWakeUpFlags
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ GetLLSWakeUpFlags
+
+
+ OpenBackDoor
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ OpenBackDoor
+
+
+ FlexNVMfeatureMethodsGrp
+ false
+ false
+
+
+ GetFlexNVMPartitionCode
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ GetFlexNVMPartitionCode
+
+
+ SetFlexNVMPartition
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ SetFlexNVMPartition
+
+
+ SetFlexRAMFunction
+ false
+ false
+ false
+ true
+ 1
+ false
+ true
+ no
+ SetFlexRAMFunction
+
+
+ MCGAutoTrim
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ MCGAutoTrim
+
+
+ VLPModeEnable
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ VLPModeEnable
+
+
+ VLPModeDisable
+ true
+ false
+ false
+ 1
+ false
+ false
+ never
+ VLPModeDisable
+
+
+ SystemReset
+ false
+ false
+ false
+ 1
+ false
+ true
+ no
+ SystemReset
+
+
+
+
+ EventModule
+ false
+ false
+ Events
+
+
+ EvntsShrdGrp
+ 1
+
+
+ SharedCommonCpuEventsInvisibleGroup
+ false
+ false
+
+
+ OnReset
+ false
+ false
+ false
+ false
+ false
+ false
+ no
+
+
+ OnResetName
+ false
+ false
+ Cpu_OnReset
+
+
+ OnNMIINT
+ true
+ false
+ false
+ false
+ false
+ true
+ never
+
+
+ OnNMIINTName
+ false
+ false
+ Cpu_OnNMIINT
+
+
+ OnHardFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnHardFaultName
+ false
+ false
+ Cpu_OnHardFault
+
+
+ OnBusFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnBusFaultName
+ false
+ false
+ Cpu_OnBusFault
+
+
+ OnUsageFault
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnUsageFaultName
+ false
+ false
+ Cpu_OnUsageFault
+
+
+ OnSupervisorCall
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnSupervisorCallName
+ false
+ false
+ Cpu_OnSupervisorCall
+
+
+ OnPendableService
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnPendableServiceName
+ false
+ false
+ Cpu_OnPendableService
+
+
+ CPUCond0
+ false
+ false
+
+
+ OnLossOfLockINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfLockINTName
+ false
+ false
+ Cpu_OnLossOfLockINT
+
+
+ LossOfClockOSC0EvntCondGrp
+ false
+ false
+
+
+ OnLossOfClockOSC0
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockOSC0Name
+ false
+ false
+ Cpu_OnLossOfClockOSC0
+
+
+ LossOfClockRTCEvntCondGrp0
+ false
+ false
+
+
+ OnLossOfClockRTC
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockRTCName
+ false
+ false
+ Cpu_OnLossOfClockRTC
+
+
+ LossOfClockOSC1EvntCondGrp
+ false
+ false
+
+
+ OnLossOfClockOSC1
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLossOfClockOSC1Name
+ false
+ false
+ Cpu_OnLossOfClockOSC1
+
+
+ OnLowVoltageINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLowVoltageINTName
+ false
+ false
+ Cpu_OnLowVoltageINT
+
+
+ OnLLSWakeUpINTCondGrp
+ false
+ false
+
+
+ OnLLSWakeUpINT
+ true
+ false
+ false
+ false
+ false
+ false
+ never
+
+
+ OnLLSWakeUpINTName
+ false
+ false
+ Cpu_OnLLSWakeUpINT
+
+
+ DDREvntCondGrp
+ false
+ false
+
+
+ OnDDRINT
+ true
+ false
+ false
+ false
+ false
+ true
+ never
+
+
+ OnDDRINTName
+ false
+ false
+ Cpu_OnDDRINT
+
+
+
+ L
+
+
+ 0
+ GNU C Compiler
+
+
+ C_CompilerIdentificationLong
+ false
+ GNU C Compiler
+ true
+
+
+ PESLsupport
+ false
+ false
+ true
+ 1
+ false
+
+
+ OSEKsupport
+ false
+ false
+ true
+ 1
+ false
+
+
+ NotRapidGrp
+ false
+ true
+
+
+ UnhandledVectorsBehavior
+ false
+ false
+ true
+ 0
+ true
+
+
+ UnhandledVectorsBehaviorFeatureGrp
+ false
+ true
+
+
+ UnhandledIntCode
+ false
+ (string list)
+ true
+
+ /* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
+ PE_DEBUGHALT();
+
+
+
+ UserInitFeatureGrp
+ false
+ true
+
+
+ UserInitGrp
+ false
+ true
+ true
+
+
+ EntryPoint_UserDecl
+ false
+ (string list)
+ true
+
+
+
+ EntryPoint_UserCodeBefore
+ false
+ (string list)
+ true
+
+
+
+ EntryPoint_UserCodeAfter
+ false
+ (string list)
+ true
+
+
+
+ NotSdk0
+ false
+ true
+
+
+ Cmplr_GenerateDebuggerFiles
+ false
+ false
+ true
+ true
+ false
+
+
+ Cmplr_GenerateCfgFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_GenerateMemFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_GenerateXmlFile
+ false
+ false
+ true
+ 0
+ true
+
+
+ Cmplr_AddStartupCond
+ false
+ true
+
+
+ NotSDK
+ false
+ true
+
+
+ Cmplr_AddStartupGrp
+ false
+ true
+ true
+
+
+ Cmplr_AddStartup
+ false
+ false
+ true
+ 0
+ true
+
+
+ C_GenerateLINKFILE
+ false
+ false
+ true
+ true
+ true
+
+
+ InitializationState
+ false
+ User_PE_initialization
+ true
+
+
+ InterruptVectorTableSizeAdjustment
+ false
+ false
+ 0
+ true
+ DEC
+
+
+ C_StackSize
+ false
+ false
+ 1024
+ true
+ HEX
+
+
+ C_HeapSize
+ false
+ false
+ 0
+ true
+ HEX
+
+
+ DefaultMemAreas
+ false
+ Click to set default >
+ true
+
+
+ C_AlraedyInitialized
+ false
+ false
+ true
+ 1
+ false
+
+
+ SdkSettingsGrp
+ false
+ true
+
+
+ VectorTableCopyRam
+ false
+ false
+ true
+ 0
+ true
+
+
+ DefaultMemInterrupts
+ false
+ false
+ true
+ 2
+ INTERNAL_FLASH
+
+
+ DefaultMemCode
+ false
+ false
+ true
+ 2
+ INTERNAL_FLASH
+
+
+ DefaultMemData
+ false
+ false
+ true
+ 0
+ INTERNAL_RAM
+
+
+ C_RomRamList
+ false
+ 5
+ true
+ true
+
+
+ C_MemoryArea0
+ false
+ true
+ true
+
+
+ C_RomRamArea0
+ false
+ false
+ true
+ true
+ true
+
+
+ C_RomRamName0
+ false
+ m_interrupts
+ true
+
+
+ C_RomRamQualifier0
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType0
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr0
+ false
+ false
+ 0
+ true
+ HEX
+
+
+
+ C_RomRamSize0
+ false
+ false
+ 488
+ true
+ HEX
+
+
+ C_RomRamGroupContent0
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea1
+ false
+ true
+ true
+
+
+ C_RomRamArea1
+ false
+ false
+ true
+ false
+ true
+
+
+ C_RomRamName1
+ false
+ m_text_000001E8
+ true
+
+
+ C_RomRamQualifier1
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType1
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr1
+ false
+ false
+ 488
+ true
+ HEX
+
+
+
+ C_RomRamSize1
+ false
+ false
+ 536
+ true
+ HEX
+
+
+ C_RomRamGroupContent1
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea2
+ false
+ true
+ true
+
+
+ C_RomRamArea2
+ false
+ false
+ true
+ true
+ true
+
+
+ C_RomRamName2
+ false
+ m_text
+ true
+
+
+ C_RomRamQualifier2
+ false
+ false
+ true
+ 1
+ RX
+
+
+ C_RomRamPhysicalType2
+ false
+ FLASH
+ true
+
+
+ C_RomRamAddr2
+ false
+ false
+ 1040
+ true
+ HEX
+
+
+
+ C_RomRamSize2
+ false
+ false
+ 1047536
+ true
+ HEX
+
+
+ C_RomRamGroupContent2
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea3
+ false
+ true
+ true
+
+
+ C_RomRamArea3
+ false
+ false
+ true
+ true
+ false
+
+
+ C_RomRamName3
+ false
+ m_data
+ true
+
+
+ C_RomRamQualifier3
+ false
+ false
+ true
+ 2
+ RW
+
+
+ C_RomRamPhysicalType3
+ false
+ RAM
+ true
+
+
+ C_RomRamAddr3
+ false
+ false
+ 536805376
+ true
+ HEX
+
+
+
+ C_RomRamSize3
+ false
+ false
+ 65536
+ true
+ HEX
+
+
+ C_RomRamGroupContent3
+ false
+ (string list)
+ true
+
+
+
+ C_MemoryArea4
+ false
+ true
+ true
+
+
+ C_RomRamArea4
+ false
+ false
+ true
+ true
+ false
+
+
+ C_RomRamName4
+ false
+ m_data_20000000
+ true
+
+
+ C_RomRamQualifier4
+ false
+ false
+ true
+ 2
+ RW
+
+
+ C_RomRamPhysicalType4
+ false
+ RAM
+ true
+
+
+ C_RomRamAddr4
+ false
+ false
+ 536870912
+ true
+ HEX
+
+
+
+ C_RomRamSize4
+ false
+ false
+ 65536
+ true
+ HEX
+
+
+ C_RomRamGroupContent4
+ false
+ (string list)
+ true
+
+
+
+ C_PECompilerSupportCondGrp
+ false
+ true
+
+
+ C_PECompilerSupport
+ false
+ true
+ true
+
+
+ C_ToolDir
+ false
+ C:\CodeWarrior for ColdFire V7.0\
+ true
+
+
+ C_GenerateMAKEFILE
+ false
+ false
+ true
+ 0
+ true
+
+
+ asmgrp
+ false
+ true
+ true
+
+
+ C_DebugInfo
+ false
+ false
+ true
+ 0
+ true
+
+
+ C_CCPars
+ false
+
+ true
+
+
+ lnkgrp
+ false
+ true
+ true
+
+
+ C_GenerateMapFile
+ false
+ false
+ true
+ true
+ true
+
+
+ C_GenerateMapFile_ListClosure
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateMapFile_ListUnusedObjects
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateMapFile_ListDWARFObjects
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateSFile
+ false
+ false
+ true
+ true
+ true
+
+
+ C_GenerateSFile_Sort
+ false
+ false
+ true
+ 1
+ false
+
+
+ C_GenerateSFile_MaxLength
+ false
+ false
+ 26
+ true
+ DEC
+
+
+ C_GenerateSFile_EOL
+ false
+ false
+ true
+ 1
+ DOS
+
+
+ C_LINKPars
+ false
+
+ true
+
+
+ NonECLIGrp
+ false
+ true
+
+
+ SystemPathsGrp
+ false
+ 0
+ true
+ true
+
+
+ UserPathsGrp
+ false
+ 0
+ true
+ false
+
+
+ LibrariesGrp
+ false
+ 0
+ true
+ false
+
+
+ UserDirectoriesGrp
+ false
+ 0
+ true
+ false
+
+
+ GNUC_ARM_Directory
+ false
+ true
+
+
+ Ansi-C
+ 0
+ HEX
+ HEX
+ HEX
+ HEX
+
+ MK70FN1M0VMJ12
+ 4
+ 32.768000000000
+
+
+
+
+
+
+
+ 1
+ RAM
+ false
+ 2
+
+
+ 0
+
+
+ 2
+ 2
+ false
+ 4
+ true
+
+
+ 0
+
+
+ 0
+
+
+ Optimizations
+ false
+ true
+ true
+
+
+ Not_for_MPC512x
+ false
+ true
+
+
+ O_NoRangeChck
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoEnableTest
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoSpeedTest
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoInitRegReset
+ false
+ false
+ true
+ 1
+ false
+
+
+ Not_for_MPC5500_MCF
+ false
+ true
+
+
+ O_PIB_full_Init
+ false
+ false
+ true
+ 1
+ false
+
+
+
+ 3
+ FLASH
+ true
+ 4
+
+
+ 0
+
+
+ 2
+ 2
+ false
+ 4
+ true
+
+
+ 0
+
+
+ 0
+
+
+ Optimizations
+ false
+ true
+ true
+
+
+ Not_for_MPC512x
+ false
+ true
+
+
+ O_NoRangeChck
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoEnableTest
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoSpeedTest
+ false
+ false
+ true
+ 1
+ false
+
+
+ O_NoInitRegReset
+ false
+ false
+ true
+ 1
+ false
+
+
+ Not_for_MPC5500_MCF
+ false
+ true
+
+
+ O_PIB_full_Init
+ false
+ false
+ true
+ 1
+ false
+
+
+
+
+
+
+
diff --git a/ProjectInfo.xml b/ProjectInfo.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c33ad0a3dbe4d5b6391c7cf5f0d3036209b752de
--- /dev/null
+++ b/ProjectInfo.xml
@@ -0,0 +1,78 @@
+
+
+
+
+ MK70FN1M0xxx12
+ 1
+
+
+ Cortex-M4
+
+
+ 128k
+ 1M
+
+
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Project_Settings\Linker_Files\ProcessorExpert.ld
+
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Static_Code\PDD\
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Static_Code\IO_Map\
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Sources\
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\
+
+
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Project_Settings\Startup_Code\
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Sources\
+
+
+
+
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\Cpu.c
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\PE_LDD.c
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\Vectors.c
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Project_Settings\Startup_Code\startup.c
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Sources\Events.c
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Sources\main.c
+
+
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\Cpu.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\IO_Map.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\PE_Const.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\PE_Error.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\PE_LDD.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Generated_Code\PE_Types.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Library\LEDs.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Library\buttons.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Library\timer.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Library\types.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Sources\Events.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Static_Code\IO_Map\MK70F12.h
+ F:\#Work\48434 Embedded Software\4 Labs\Lab 0\Template\Lab0\Static_Code\PDD\PDD_Types.h
+
+
+
+
+
diff --git a/Project_Settings/Debugger/Lab0_Debug_PNE.launch b/Project_Settings/Debugger/Lab0_Debug_PNE.launch
new file mode 100644
index 0000000000000000000000000000000000000000..2d96ae468b1f87d7b6a15d51ffa13b3d53ba9697
--- /dev/null
+++ b/Project_Settings/Debugger/Lab0_Debug_PNE.launch
@@ -0,0 +1,60 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Project_Settings/Linker_Files/ProcessorExpert.ld b/Project_Settings/Linker_Files/ProcessorExpert.ld
new file mode 100644
index 0000000000000000000000000000000000000000..4efdc0712593791e39784da357190171397e6cdf
--- /dev/null
+++ b/Project_Settings/Linker_Files/ProcessorExpert.ld
@@ -0,0 +1,224 @@
+/* ################################################################### */
+/*##
+/*## This component module is generated by Processor Expert. Do not modify it. */
+/*## */
+/*## Filename : ProcessorExpert.ld */
+/*## */
+/*## Project : Lab0 */
+/*## */
+/*## Processor : MK70FN1M0VMJ12 */
+/*## */
+/*## Compiler : GNU C Compiler */
+/*## */
+/*## Date/Time : 2018-07-15, 23:43, # CodeGen: 0 */
+/*## */
+/*## Abstract : */
+/*## */
+/*## This file is used by the linker. It describes files to be linked, */
+/*## memory ranges, stack size, etc. For detailed description about linker */
+/*## command files see compiler documentation. This file is generated by default. */
+/*## You can switch off generation by setting the property "Generate linker file = no" */
+/*## in the "Build options" tab of the CPU component and then modify this file as needed. */
+/*##
+/*## */
+/*## ###################################################################*/
+
+
+/* Entry Point */
+ENTRY(__thumb_startup)
+
+/* Highest address of the user mode stack */
+_estack = 0x20000000; /* end of m_data */
+__SP_INIT = _estack;
+__stack = _estack;
+
+/* Generate a link error if heap and stack don't fit into RAM */
+__heap_size = 0x00; /* required amount of heap */
+__stack_size = 0x0400; /* required amount of stack */
+
+MEMORY {
+ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000001E8
+ m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0
+ m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
+ m_data_20000000 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000
+ m_cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into INTERNAL_FLASH */
+ .interrupts :
+ {
+ __vector_table = .;
+ . = ALIGN(4);
+ KEEP(*(.vectortable)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .cfmprotect :
+ {
+ . = ALIGN(4);
+ KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */
+ . = ALIGN(4);
+ } > m_cfmprotrom
+
+ /* The program code and other data goes into INTERNAL_FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+
+ _etext = .; /* define a global symbols at end of code */
+ } > m_text
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ ___ROM_AT = .;
+ } > m_text
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data : AT(___ROM_AT)
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+
+ _edata = .; /* define a global symbol at data end */
+ } > m_data
+
+ ___data_size = _edata - _sdata;
+ ___m_data_20000000_ROMStart = ___ROM_AT + SIZEOF(.data);
+ .m_data_20000000 : AT(___m_data_20000000_ROMStart)
+ {
+ . = ALIGN(4);
+ ___m_data_20000000_RAMStart = .;
+ *(.m_data_20000000) /* This is an User defined section */
+ ___m_data_20000000_RAMEnd = .;
+ . = ALIGN(4);
+ } > m_data_20000000
+ ___m_data_20000000_ROMSize = ___m_data_20000000_RAMEnd - ___m_data_20000000_RAMStart;
+
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ __START_BSS = .;
+ PROVIDE ( __bss_start__ = __START_BSS );
+
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ __END_BSS = .;
+ PROVIDE ( __bss_end__ = __END_BSS );
+ } > m_data
+
+ _romp_at = ___ROM_AT + SIZEOF(.data) +SIZEOF(.m_data_20000000);
+ .romp : AT(_romp_at)
+ {
+ __S_romp = _romp_at;
+ LONG(___ROM_AT);
+ LONG(_sdata);
+ LONG(___data_size);
+ LONG(___m_data_20000000_ROMStart);
+ LONG(___m_data_20000000_RAMStart);
+ LONG(___m_data_20000000_ROMSize);
+ LONG(0);
+ LONG(0);
+ LONG(0);
+ } > m_data
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ __heap_addr = .;
+ __HeapBase = .;
+ . = . + __heap_size;
+ __HeapLimit = .;
+ . = . + __stack_size;
+ . = ALIGN(4);
+ } > m_data
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/Project_Settings/Startup_Code/startup.c b/Project_Settings/Startup_Code/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..4cec8ccd163446b20ff7c455b564d15df788c1c4
--- /dev/null
+++ b/Project_Settings/Startup_Code/startup.c
@@ -0,0 +1,240 @@
+/* GNUC Startup library
+ * Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved.
+ *
+ * $Date: 2011/09/21 06:41:34 $
+ * $Revision: 1.4 $
+ */
+
+
+/*
+ * startup.c - entry-point for ARM programs
+ *
+ */
+#include
+#include
+#include "IO_Map.h"
+
+#ifndef __ATOLLIC__
+extern void _start(void);
+#else
+extern void __libc_init_array();
+extern void main();
+#endif
+extern char __SP_INIT[];
+
+extern void __init_registers();
+extern void __init_hardware();
+extern void __init_user();
+
+extern void __copy_rom_sections_to_ram(void);
+
+/* format of the ROM table info entry ... */
+typedef struct RomInfo {
+ unsigned long Source;
+ unsigned long Target;
+ unsigned long Size;
+} RomInfo;
+
+extern RomInfo __S_romp[] __attribute__((weak)); /* linker defined symbol */
+
+/*
+ * Routine to copy a single section from ROM to RAM ...
+ */
+void __copy_rom_section(unsigned long dst, unsigned long src, unsigned long size)
+{
+ unsigned long len = size;
+
+ const unsigned int size_int = sizeof(int);
+ const unsigned int mask_int = sizeof(int)-1;
+
+ const unsigned int size_short = sizeof(short);
+ const unsigned int mask_short = sizeof(short)-1;
+
+ const unsigned int size_char = sizeof(char);
+
+ if( dst == src || size == 0)
+ {
+ return;
+ }
+
+
+ while( len > 0)
+ {
+
+ if( !(src & mask_int) && !(dst & mask_int) && len >= size_int)
+ {
+ *((int *)dst) = *((int*)src);
+ dst += size_int;
+ src += size_int;
+ len -= size_int;
+ }
+ else if( !(src & mask_short) && !(dst & mask_short) && len >= size_short)
+ {
+ *((short *)dst) = *((short*)src);
+ dst += size_short;
+ src += size_short;
+ len -= size_short;
+ }
+ else
+ {
+ *((char *)dst) = *((char*)src);
+ dst += size_char;
+ src += size_char;
+ len -= size_char;
+ }
+ }
+}
+
+/*
+ * Routine that copies all sections the user marked as ROM into
+ * their target RAM addresses ...
+ *
+ * __S_romp is defined in the linker command file
+ * It is a table of RomInfo
+ * structures. The final entry in the table has all-zero
+ * fields.
+ */
+void __copy_rom_sections_to_ram(void)
+{
+
+ int index;
+
+ if (__S_romp == 0L) return;
+
+ /*
+ * Go through the entire table, copying sections from ROM to RAM.
+ */
+ for (index = 0;
+ __S_romp[index].Source != 0 ||
+ __S_romp[index].Target != 0 ||
+ __S_romp[index].Size != 0;
+ ++index)
+ {
+ __copy_rom_section( __S_romp[index].Target,
+ __S_romp[index].Source,
+ __S_romp[index].Size );
+
+ }
+}
+
+#ifdef __ATOLLIC__
+static void zero_fill_bss(void)
+{
+ extern char __START_BSS[];
+ extern char __END_BSS[];
+
+ unsigned long len = __END_BSS - __START_BSS;
+ unsigned long dst = (unsigned long) __START_BSS;
+
+ const int size_int = sizeof(int);
+ const int mask_int = sizeof(int)-1;
+
+ const int size_short = sizeof(short);
+ const int mask_short = sizeof(short)-1;
+
+ const int size_char = sizeof(char);
+
+ if( len == 0)
+ {
+ return;
+ }
+
+
+ while( len > 0)
+ {
+ if( !(dst & mask_int) && len >= size_int)
+ {
+ *((int *)dst) = 0;
+ dst += size_int;
+ len -= size_int;
+ }
+ else if( !(dst & mask_short) && len >= size_short)
+ {
+ *((short *)dst) = 0;
+ dst += size_short;
+ len -= size_short;
+ }
+ else
+ {
+ *((char *)dst) = 0;
+ dst += size_char;
+ len -= size_char;
+ }
+ }
+}
+#endif
+
+void __attribute__ ((weak)) __init_registers(void)
+{
+ #if defined(SCB_CPACR)
+ /* Initialize FPU */
+ SCB_CPACR |= SCB_CPACR_CP10(3U) | SCB_CPACR_CP11(3U);
+ #endif
+
+}
+
+void __attribute__ ((weak)) __init_hardware(void)
+{
+
+}
+
+void __attribute__ ((weak)) __init_user(void)
+{
+
+}
+
+
+/* To match iar debugger expectation */
+void __iar_program_start(void);
+void __thumb_startup(void);
+void __iar_program_start()
+{
+ __thumb_startup();
+}
+
+__attribute__((naked)) void __thumb_startup(void)
+{
+int addr = (int)__SP_INIT;
+
+ /* setup the stack before we attempt anything else
+ skip stack setup if __SP_INIT is 0
+ assume sp is already setup. */
+ __asm (
+ "mov r0,%0\n\t"
+ "cmp r0,#0\n\t"
+ "beq skip_sp\n\t"
+ "mov sp,r0\n\t"
+ "sub sp,#4\n\t"
+ "mov r0,#0\n\t"
+ "mvn r0,r0\n\t"
+ "str r0,[sp,#0]\n\t"
+ "add sp,#4\n\t"
+ "skip_sp:\n\t"
+ ::"r"(addr));
+
+ /* Setup registers */
+ __init_registers();
+
+ /* setup hardware */
+ __init_hardware();
+
+ /* SUPPORT_ROM_TO_RAM */
+ __copy_rom_sections_to_ram();
+
+ /* initializations before main, user specific */
+ __init_user();
+
+#ifndef __ATOLLIC__
+ _start();
+#else
+ /* zero-fill the .bss section */
+ zero_fill_bss();
+ /* Run static constructors */
+ __libc_init_array();
+ main();
+#endif
+
+ /* should never get here */
+ while (1);
+
+}
diff --git a/Sources/main.c b/Sources/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..48a7df187aed2a8da34df1057104e17462adfa56
--- /dev/null
+++ b/Sources/main.c
@@ -0,0 +1,84 @@
+/*!
+** @file
+** @version 1.0
+** @brief
+** Main module.
+** This module implements a simple 12-hour clock.
+** It time-stamps button pushes and stores them in a FIFO used a packed representation.
+*/
+/*!
+** @addtogroup main_module main module documentation
+** @{
+*/
+/* MODULE main */
+
+
+// CPU module - contains low level hardware initialization routines
+#include "Cpu.h"
+#include "PE_Types.h"
+#include "PE_Error.h"
+#include "PE_Const.h"
+#include "IO_Map.h"
+
+// Simple timer
+#include "timer.h"
+
+// Button functions
+#include "buttons.h"
+
+// LED functions
+#include "LEDs.h"
+
+// The packed time representation
+
+// 15 12 11 6 5 0
+// |----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|----|
+// | hours | minutes | seconds |
+
+typedef uint16_t PackedTime_t;
+
+// ***
+// You will need to create a FIFO object with a size suitable to store 10 time-stamps using the packed time representation.
+// ***
+
+static void OneSecondElapsed(void)
+{
+ LEDs_Toggle(LED_BLUE);
+ // One second has elapsed - update the time here
+}
+
+static void Button1Pressed(void)
+{
+ LEDs_Toggle(LED_ORANGE);
+ // The button has been pressed - put a time-stamp into the FIFO
+}
+
+static void TowerInit(void)
+{
+ PE_low_level_init();
+ Timer_Init(OneSecondElapsed);
+ Buttons_Init(Button1Pressed);
+ LEDs_Init();
+ __EI();
+}
+
+/*lint -save -e970 Disable MISRA rule (6.3) checking. */
+int main(void)
+/*lint -restore Enable MISRA rule (6.3) checking. */
+{
+ /* Write your local variable definition here */
+
+ /*** Processor Expert internal initialization. DON'T REMOVE THIS CODE!!! ***/
+ PE_low_level_init();
+ /*** End of Processor Expert internal initialization. ***/
+ TowerInit();
+ /* Write your code here */
+ for (;;)
+ {
+ }
+}
+
+/* END main */
+/*!
+** @}
+*/
diff --git a/Static_Code/IO_Map/MK70F12.h b/Static_Code/IO_Map/MK70F12.h
new file mode 100644
index 0000000000000000000000000000000000000000..b5de9dc372a59959abe435b7aa9c38e5cd543892
--- /dev/null
+++ b/Static_Code/IO_Map/MK70F12.h
@@ -0,0 +1,20392 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K70P256M150SF3RM, Rev. 2, Dec 2011
+** Version: rev. 1.12, 2013-10-29
+** Build: b150309
+**
+** Abstract:
+** This header file implements peripheral memory map for MK70F12
+** processor.
+**
+** Copyright (c) 1997 - 2013 Freescale Semiconductor, Inc.
+** All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-08-12)
+** Initial version.
+** - rev. 1.1 (2011-09-23)
+** Fixed number of slave registers of AXBS module.
+** - rev. 1.2 (2011-11-03)
+** Registers updated according to the new reference manual revision - Rev. 1, Oct 2011
+** Registers of the following modules have been updated - CAN, DDR, I2S, LCDC, MCG, MPU, NFC, RCM, RTC, SIM, USBHS, WDOG
+** - rev. 1.3 (2011-11-10)
+** Support of ARM Keil compiler added.
+** - rev. 1.4 (2011-11-18)
+** SDHC - bit group WRBRSTLEN from the SDHC_WML register removed.
+** - rev. 1.5 (2012-01-04)
+** Registers updated according to the new reference manual revision - Rev. 2, Dec 2011
+** EWM - INTEN bit in EWM_CTRL register has been added.
+** PDB - register PDB_PO0EN renamed to PRB_POEN.
+** PMC - BGEN bit in PMC_REGSC register has been removed.
+** SIM - several changes in SCGC registers. Bit USBHS in SOPT2 register removed.
+** UART - new bits RXOFE in regiter CFIFO and RXOF in register SFIFO.
+** DRY - bit THYD in CR register renamed to THYS. Bit group KSL in LR register removed.
+** LCDC - bits GWLPM in LSR register, ERR_RES_EN, GW_ERR_RES_EN in LIER and ERR_RES, GW_ERR_RES in LISR removed.
+** - rev. 1.6 (2012-04-13)
+** Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
+** Added new #define symbols _BASE_PTRS.
+** - rev. 1.7 (2012-07-09)
+** UART1 - Fixed register definition - ISO7816 registers added.
+** - rev. 1.8 (2012-09-17)
+** DRY module removed.
+** - rev. 1.9 (2012-10-19)
+** RTC - security related registers removed.
+** - rev. 1.10 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.11 (2013-06-24)
+** MPU - missing region descriptor registers added.
+** SCB - register CPACR added.
+** - rev. 1.12 (2013-10-29)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK70F12.h
+ * @version 1.12
+ * @date 2013-10-29
+ * @brief Peripheral memory map for MK70F12
+ *
+ * This header file implements peripheral memory map for MK70F12 processor.
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MCU_MK70F12) && !defined(MCU_MK70F15) /* Check if memory map has not been already included */
+#define MCU_MK70F12
+#define MCU_MK70F15
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK70F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x000Cu
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum {
+ INT_Initial_Stack_Pointer = 0, /**< Initial stack pointer */
+ INT_Initial_Program_Counter = 1, /**< Initial program counter */
+ INT_NMI = 2, /**< Non-maskable interrupt */
+ INT_Hard_Fault = 3, /**< Hard fault exception */
+ INT_Mem_Manage_Fault = 4, /**< Memory Manage Fault */
+ INT_Bus_Fault = 5, /**< Bus fault exception */
+ INT_Usage_Fault = 6, /**< Usage fault exception */
+ INT_Reserved7 = 7, /**< Reserved interrupt 7 */
+ INT_Reserved8 = 8, /**< Reserved interrupt 8 */
+ INT_Reserved9 = 9, /**< Reserved interrupt 9 */
+ INT_Reserved10 = 10, /**< Reserved interrupt 10 */
+ INT_SVCall = 11, /**< A supervisor call exception */
+ INT_DebugMonitor = 12, /**< Debug Monitor */
+ INT_Reserved13 = 13, /**< Reserved interrupt 13 */
+ INT_PendableSrvReq = 14, /**< PendSV exception - request for system level service */
+ INT_SysTick = 15, /**< SysTick interrupt */
+ INT_DMA0_DMA16 = 16, /**< DMA channel 0/16 transfer complete interrupt */
+ INT_DMA1_DMA17 = 17, /**< DMA channel 1/17 transfer complete interrupt */
+ INT_DMA2_DMA18 = 18, /**< DMA channel 2/18 transfer complete interrupt */
+ INT_DMA3_DMA19 = 19, /**< DMA channel 3/19 transfer complete interrupt */
+ INT_DMA4_DMA20 = 20, /**< DMA channel 4/20 transfer complete interrupt */
+ INT_DMA5_DMA21 = 21, /**< DMA channel 5/21 transfer complete interrupt */
+ INT_DMA6_DMA22 = 22, /**< DMA channel 6/22 transfer complete interrupt */
+ INT_DMA7_DMA23 = 23, /**< DMA channel 7/23 transfer complete interrupt */
+ INT_DMA8_DMA24 = 24, /**< DMA channel 8/24 transfer complete interrupt */
+ INT_DMA9_DMA25 = 25, /**< DMA channel 9/25 transfer complete interrupt */
+ INT_DMA10_DMA26 = 26, /**< DMA channel 10/26 transfer complete interrupt */
+ INT_DMA11_DMA27 = 27, /**< DMA channel 11/27 transfer complete interrupt */
+ INT_DMA12_DMA28 = 28, /**< DMA channel 12/28 transfer complete interrupt */
+ INT_DMA13_DMA29 = 29, /**< DMA channel 13/29 transfer complete interrupt */
+ INT_DMA14_DMA30 = 30, /**< DMA channel 14/30 transfer complete interrupt */
+ INT_DMA15_DMA31 = 31, /**< DMA channel 15/31 transfer complete interrupt */
+ INT_DMA_Error = 32, /**< DMA error interrupt */
+ INT_MCM = 33, /**< Normal interrupt */
+ INT_FTFE = 34, /**< FTFE interrupt */
+ INT_Read_Collision = 35, /**< Read collision interrupt */
+ INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */
+ INT_LLW = 37, /**< Low Leakage Wakeup */
+ INT_Watchdog = 38, /**< WDOG interrupt */
+ INT_RNG = 39, /**< RNGA interrupt */
+ INT_I2C0 = 40, /**< I2C0 interrupt */
+ INT_I2C1 = 41, /**< I2C1 interrupt */
+ INT_SPI0 = 42, /**< SPI0 interrupt */
+ INT_SPI1 = 43, /**< SPI1 interrupt */
+ INT_SPI2 = 44, /**< SPI2 interrupt */
+ INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd message buffers interrupt */
+ INT_CAN0_Bus_Off = 46, /**< CAN0 bus off interrupt */
+ INT_CAN0_Error = 47, /**< CAN0 error interrupt */
+ INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx warning interrupt */
+ INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx warning interrupt */
+ INT_CAN0_Wake_Up = 50, /**< CAN0 wake up interrupt */
+ INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */
+ INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */
+ INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd message buffers interrupt */
+ INT_CAN1_Bus_Off = 54, /**< CAN1 bus off interrupt */
+ INT_CAN1_Error = 55, /**< CAN1 error interrupt */
+ INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx warning interrupt */
+ INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx warning interrupt */
+ INT_CAN1_Wake_Up = 58, /**< CAN1 wake up interrupt */
+ INT_Reserved59 = 59, /**< Reserved interrupt 59 */
+ INT_UART0_LON = 60, /**< UART0 LON interrupt */
+ INT_UART0_RX_TX = 61, /**< UART0 receive/transmit interrupt */
+ INT_UART0_ERR = 62, /**< UART0 error interrupt */
+ INT_UART1_RX_TX = 63, /**< UART1 receive/transmit interrupt */
+ INT_UART1_ERR = 64, /**< UART1 error interrupt */
+ INT_UART2_RX_TX = 65, /**< UART2 receive/transmit interrupt */
+ INT_UART2_ERR = 66, /**< UART2 error interrupt */
+ INT_UART3_RX_TX = 67, /**< UART3 receive/transmit interrupt */
+ INT_UART3_ERR = 68, /**< UART3 error interrupt */
+ INT_UART4_RX_TX = 69, /**< UART4 receive/transmit interrupt */
+ INT_UART4_ERR = 70, /**< UART4 error interrupt */
+ INT_UART5_RX_TX = 71, /**< UART5 receive/transmit interrupt */
+ INT_UART5_ERR = 72, /**< UART5 error interrupt */
+ INT_ADC0 = 73, /**< ADC0 interrupt */
+ INT_ADC1 = 74, /**< ADC1 interrupt */
+ INT_CMP0 = 75, /**< CMP0 interrupt */
+ INT_CMP1 = 76, /**< CMP1 interrupt */
+ INT_CMP2 = 77, /**< CMP2 interrupt */
+ INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */
+ INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */
+ INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */
+ INT_CMT = 81, /**< CMT interrupt */
+ INT_RTC = 82, /**< RTC interrupt */
+ INT_RTC_Seconds = 83, /**< RTC seconds interrupt */
+ INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */
+ INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */
+ INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */
+ INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */
+ INT_PDB0 = 88, /**< PDB0 interrupt */
+ INT_USB0 = 89, /**< USB0 interrupt */
+ INT_USBDCD = 90, /**< USBDCD interrupt */
+ INT_ENET_1588_Timer = 91, /**< Ethernet MAC IEEE 1588 timer interrupt */
+ INT_ENET_Transmit = 92, /**< Ethernet MAC transmit interrupt */
+ INT_ENET_Receive = 93, /**< Ethernet MAC receive interrupt */
+ INT_ENET_Error = 94, /**< Ethernet MAC error and miscelaneous interrupt */
+ INT_Reserved95 = 95, /**< Reserved interrupt 95 */
+ INT_SDHC = 96, /**< SDHC interrupt */
+ INT_DAC0 = 97, /**< DAC0 interrupt */
+ INT_DAC1 = 98, /**< DAC1 interrupt */
+ INT_TSI0 = 99, /**< TSI0 interrupt */
+ INT_MCG = 100, /**< MCG interrupt */
+ INT_LPTimer = 101, /**< LPTimer interrupt */
+ INT_Reserved102 = 102, /**< Reserved interrupt 102 */
+ INT_PORTA = 103, /**< Port A interrupt */
+ INT_PORTB = 104, /**< Port B interrupt */
+ INT_PORTC = 105, /**< Port C interrupt */
+ INT_PORTD = 106, /**< Port D interrupt */
+ INT_PORTE = 107, /**< Port E interrupt */
+ INT_PORTF = 108, /**< Port F interrupt */
+ INT_DDR = 109, /**< DDR interrupt */
+ INT_SWI = 110, /**< Software interrupt */
+ INT_NFC = 111, /**< NAND flash controller interrupt */
+ INT_USBHS = 112, /**< USB high speed OTG interrupt */
+ INT_LCD = 113, /**< Graphical LCD interrupt */
+ INT_CMP3 = 114, /**< CMP3 interrupt */
+ INT_Reserved115 = 115, /**< Reserved interrupt 115 */
+ INT_Reserved116 = 116, /**< Reserved interrupt 116 */
+ INT_FTM3 = 117, /**< FTM3 fault, overflow and channels interrupt */
+ INT_ADC2 = 118, /**< ADC2 interrupt */
+ INT_ADC3 = 119, /**< ADC3 interrupt */
+ INT_I2S1_Tx = 120, /**< I2S1 transmit interrupt */
+ INT_I2S1_Rx = 121 /**< I2S1 receive interrupt */
+} IRQInterruptIndex;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Peripheral type defines
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_defines Peripheral type defines
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral ADC
+ * @{
+ */
+
+/** ADC - Peripheral register structure */
+typedef struct ADC_MemMap {
+ uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint32_t PGA; /**< ADC PGA register, offset: 0x50 */
+ uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} volatile *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_PGA_REG(base) ((base)->PGA)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA)
+#define AIPS_PACRA_REG(base) ((base)->PACRA)
+#define AIPS_PACRB_REG(base) ((base)->PACRB)
+#define AIPS_PACRC_REG(base) ((base)->PACRC)
+#define AIPS_PACRD_REG(base) ((base)->PACRD)
+#define AIPS_PACRE_REG(base) ((base)->PACRE)
+#define AIPS_PACRF_REG(base) ((base)->PACRF)
+#define AIPS_PACRG_REG(base) ((base)->PACRG)
+#define AIPS_PACRH_REG(base) ((base)->PACRH)
+#define AIPS_PACRI_REG(base) ((base)->PACRI)
+#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
+#define AIPS_PACRK_REG(base) ((base)->PACRK)
+#define AIPS_PACRL_REG(base) ((base)->PACRL)
+#define AIPS_PACRM_REG(base) ((base)->PACRM)
+#define AIPS_PACRN_REG(base) ((base)->PACRN)
+#define AIPS_PACRO_REG(base) ((base)->PACRO)
+#define AIPS_PACRP_REG(base) ((base)->PACRP)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL7_MASK 0x1u
+#define AIPS_MPRA_MPL7_SHIFT 0
+#define AIPS_MPRA_MTW7_MASK 0x2u
+#define AIPS_MPRA_MTW7_SHIFT 1
+#define AIPS_MPRA_MTR7_MASK 0x4u
+#define AIPS_MPRA_MTR7_SHIFT 2
+#define AIPS_MPRA_MPL6_MASK 0x10u
+#define AIPS_MPRA_MPL6_SHIFT 4
+#define AIPS_MPRA_MTW6_MASK 0x20u
+#define AIPS_MPRA_MTW6_SHIFT 5
+#define AIPS_MPRA_MTR6_MASK 0x40u
+#define AIPS_MPRA_MTR6_SHIFT 6
+#define AIPS_MPRA_MPL5_MASK 0x100u
+#define AIPS_MPRA_MPL5_SHIFT 8
+#define AIPS_MPRA_MTW5_MASK 0x200u
+#define AIPS_MPRA_MTW5_SHIFT 9
+#define AIPS_MPRA_MTR5_MASK 0x400u
+#define AIPS_MPRA_MTR5_SHIFT 10
+#define AIPS_MPRA_MPL4_MASK 0x1000u
+#define AIPS_MPRA_MPL4_SHIFT 12
+#define AIPS_MPRA_MTW4_MASK 0x2000u
+#define AIPS_MPRA_MTW4_SHIFT 13
+#define AIPS_MPRA_MTR4_MASK 0x4000u
+#define AIPS_MPRA_MTR4_SHIFT 14
+#define AIPS_MPRA_MPL3_MASK 0x10000u
+#define AIPS_MPRA_MPL3_SHIFT 16
+#define AIPS_MPRA_MTW3_MASK 0x20000u
+#define AIPS_MPRA_MTW3_SHIFT 17
+#define AIPS_MPRA_MTR3_MASK 0x40000u
+#define AIPS_MPRA_MTR3_SHIFT 18
+#define AIPS_MPRA_MPL2_MASK 0x100000u
+#define AIPS_MPRA_MPL2_SHIFT 20
+#define AIPS_MPRA_MTW2_MASK 0x200000u
+#define AIPS_MPRA_MTW2_SHIFT 21
+#define AIPS_MPRA_MTR2_MASK 0x400000u
+#define AIPS_MPRA_MTR2_SHIFT 22
+#define AIPS_MPRA_MPL1_MASK 0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT 24
+#define AIPS_MPRA_MTW1_MASK 0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT 25
+#define AIPS_MPRA_MTR1_MASK 0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT 26
+#define AIPS_MPRA_MPL0_MASK 0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT 28
+#define AIPS_MPRA_MTW0_MASK 0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT 29
+#define AIPS_MPRA_MTR0_MASK 0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT 30
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK 0x1u
+#define AIPS_PACRA_TP7_SHIFT 0
+#define AIPS_PACRA_WP7_MASK 0x2u
+#define AIPS_PACRA_WP7_SHIFT 1
+#define AIPS_PACRA_SP7_MASK 0x4u
+#define AIPS_PACRA_SP7_SHIFT 2
+#define AIPS_PACRA_TP6_MASK 0x10u
+#define AIPS_PACRA_TP6_SHIFT 4
+#define AIPS_PACRA_WP6_MASK 0x20u
+#define AIPS_PACRA_WP6_SHIFT 5
+#define AIPS_PACRA_SP6_MASK 0x40u
+#define AIPS_PACRA_SP6_SHIFT 6
+#define AIPS_PACRA_TP5_MASK 0x100u
+#define AIPS_PACRA_TP5_SHIFT 8
+#define AIPS_PACRA_WP5_MASK 0x200u
+#define AIPS_PACRA_WP5_SHIFT 9
+#define AIPS_PACRA_SP5_MASK 0x400u
+#define AIPS_PACRA_SP5_SHIFT 10
+#define AIPS_PACRA_TP4_MASK 0x1000u
+#define AIPS_PACRA_TP4_SHIFT 12
+#define AIPS_PACRA_WP4_MASK 0x2000u
+#define AIPS_PACRA_WP4_SHIFT 13
+#define AIPS_PACRA_SP4_MASK 0x4000u
+#define AIPS_PACRA_SP4_SHIFT 14
+#define AIPS_PACRA_TP3_MASK 0x10000u
+#define AIPS_PACRA_TP3_SHIFT 16
+#define AIPS_PACRA_WP3_MASK 0x20000u
+#define AIPS_PACRA_WP3_SHIFT 17
+#define AIPS_PACRA_SP3_MASK 0x40000u
+#define AIPS_PACRA_SP3_SHIFT 18
+#define AIPS_PACRA_TP2_MASK 0x100000u
+#define AIPS_PACRA_TP2_SHIFT 20
+#define AIPS_PACRA_WP2_MASK 0x200000u
+#define AIPS_PACRA_WP2_SHIFT 21
+#define AIPS_PACRA_SP2_MASK 0x400000u
+#define AIPS_PACRA_SP2_SHIFT 22
+#define AIPS_PACRA_TP1_MASK 0x1000000u
+#define AIPS_PACRA_TP1_SHIFT 24
+#define AIPS_PACRA_WP1_MASK 0x2000000u
+#define AIPS_PACRA_WP1_SHIFT 25
+#define AIPS_PACRA_SP1_MASK 0x4000000u
+#define AIPS_PACRA_SP1_SHIFT 26
+#define AIPS_PACRA_TP0_MASK 0x10000000u
+#define AIPS_PACRA_TP0_SHIFT 28
+#define AIPS_PACRA_WP0_MASK 0x20000000u
+#define AIPS_PACRA_WP0_SHIFT 29
+#define AIPS_PACRA_SP0_MASK 0x40000000u
+#define AIPS_PACRA_SP0_SHIFT 30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK 0x1u
+#define AIPS_PACRB_TP7_SHIFT 0
+#define AIPS_PACRB_WP7_MASK 0x2u
+#define AIPS_PACRB_WP7_SHIFT 1
+#define AIPS_PACRB_SP7_MASK 0x4u
+#define AIPS_PACRB_SP7_SHIFT 2
+#define AIPS_PACRB_TP6_MASK 0x10u
+#define AIPS_PACRB_TP6_SHIFT 4
+#define AIPS_PACRB_WP6_MASK 0x20u
+#define AIPS_PACRB_WP6_SHIFT 5
+#define AIPS_PACRB_SP6_MASK 0x40u
+#define AIPS_PACRB_SP6_SHIFT 6
+#define AIPS_PACRB_TP5_MASK 0x100u
+#define AIPS_PACRB_TP5_SHIFT 8
+#define AIPS_PACRB_WP5_MASK 0x200u
+#define AIPS_PACRB_WP5_SHIFT 9
+#define AIPS_PACRB_SP5_MASK 0x400u
+#define AIPS_PACRB_SP5_SHIFT 10
+#define AIPS_PACRB_TP4_MASK 0x1000u
+#define AIPS_PACRB_TP4_SHIFT 12
+#define AIPS_PACRB_WP4_MASK 0x2000u
+#define AIPS_PACRB_WP4_SHIFT 13
+#define AIPS_PACRB_SP4_MASK 0x4000u
+#define AIPS_PACRB_SP4_SHIFT 14
+#define AIPS_PACRB_TP3_MASK 0x10000u
+#define AIPS_PACRB_TP3_SHIFT 16
+#define AIPS_PACRB_WP3_MASK 0x20000u
+#define AIPS_PACRB_WP3_SHIFT 17
+#define AIPS_PACRB_SP3_MASK 0x40000u
+#define AIPS_PACRB_SP3_SHIFT 18
+#define AIPS_PACRB_TP2_MASK 0x100000u
+#define AIPS_PACRB_TP2_SHIFT 20
+#define AIPS_PACRB_WP2_MASK 0x200000u
+#define AIPS_PACRB_WP2_SHIFT 21
+#define AIPS_PACRB_SP2_MASK 0x400000u
+#define AIPS_PACRB_SP2_SHIFT 22
+#define AIPS_PACRB_TP1_MASK 0x1000000u
+#define AIPS_PACRB_TP1_SHIFT 24
+#define AIPS_PACRB_WP1_MASK 0x2000000u
+#define AIPS_PACRB_WP1_SHIFT 25
+#define AIPS_PACRB_SP1_MASK 0x4000000u
+#define AIPS_PACRB_SP1_SHIFT 26
+#define AIPS_PACRB_TP0_MASK 0x10000000u
+#define AIPS_PACRB_TP0_SHIFT 28
+#define AIPS_PACRB_WP0_MASK 0x20000000u
+#define AIPS_PACRB_WP0_SHIFT 29
+#define AIPS_PACRB_SP0_MASK 0x40000000u
+#define AIPS_PACRB_SP0_SHIFT 30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK 0x1u
+#define AIPS_PACRC_TP7_SHIFT 0
+#define AIPS_PACRC_WP7_MASK 0x2u
+#define AIPS_PACRC_WP7_SHIFT 1
+#define AIPS_PACRC_SP7_MASK 0x4u
+#define AIPS_PACRC_SP7_SHIFT 2
+#define AIPS_PACRC_TP6_MASK 0x10u
+#define AIPS_PACRC_TP6_SHIFT 4
+#define AIPS_PACRC_WP6_MASK 0x20u
+#define AIPS_PACRC_WP6_SHIFT 5
+#define AIPS_PACRC_SP6_MASK 0x40u
+#define AIPS_PACRC_SP6_SHIFT 6
+#define AIPS_PACRC_TP5_MASK 0x100u
+#define AIPS_PACRC_TP5_SHIFT 8
+#define AIPS_PACRC_WP5_MASK 0x200u
+#define AIPS_PACRC_WP5_SHIFT 9
+#define AIPS_PACRC_SP5_MASK 0x400u
+#define AIPS_PACRC_SP5_SHIFT 10
+#define AIPS_PACRC_TP4_MASK 0x1000u
+#define AIPS_PACRC_TP4_SHIFT 12
+#define AIPS_PACRC_WP4_MASK 0x2000u
+#define AIPS_PACRC_WP4_SHIFT 13
+#define AIPS_PACRC_SP4_MASK 0x4000u
+#define AIPS_PACRC_SP4_SHIFT 14
+#define AIPS_PACRC_TP3_MASK 0x10000u
+#define AIPS_PACRC_TP3_SHIFT 16
+#define AIPS_PACRC_WP3_MASK 0x20000u
+#define AIPS_PACRC_WP3_SHIFT 17
+#define AIPS_PACRC_SP3_MASK 0x40000u
+#define AIPS_PACRC_SP3_SHIFT 18
+#define AIPS_PACRC_TP2_MASK 0x100000u
+#define AIPS_PACRC_TP2_SHIFT 20
+#define AIPS_PACRC_WP2_MASK 0x200000u
+#define AIPS_PACRC_WP2_SHIFT 21
+#define AIPS_PACRC_SP2_MASK 0x400000u
+#define AIPS_PACRC_SP2_SHIFT 22
+#define AIPS_PACRC_TP1_MASK 0x1000000u
+#define AIPS_PACRC_TP1_SHIFT 24
+#define AIPS_PACRC_WP1_MASK 0x2000000u
+#define AIPS_PACRC_WP1_SHIFT 25
+#define AIPS_PACRC_SP1_MASK 0x4000000u
+#define AIPS_PACRC_SP1_SHIFT 26
+#define AIPS_PACRC_TP0_MASK 0x10000000u
+#define AIPS_PACRC_TP0_SHIFT 28
+#define AIPS_PACRC_WP0_MASK 0x20000000u
+#define AIPS_PACRC_WP0_SHIFT 29
+#define AIPS_PACRC_SP0_MASK 0x40000000u
+#define AIPS_PACRC_SP0_SHIFT 30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK 0x1u
+#define AIPS_PACRD_TP7_SHIFT 0
+#define AIPS_PACRD_WP7_MASK 0x2u
+#define AIPS_PACRD_WP7_SHIFT 1
+#define AIPS_PACRD_SP7_MASK 0x4u
+#define AIPS_PACRD_SP7_SHIFT 2
+#define AIPS_PACRD_TP6_MASK 0x10u
+#define AIPS_PACRD_TP6_SHIFT 4
+#define AIPS_PACRD_WP6_MASK 0x20u
+#define AIPS_PACRD_WP6_SHIFT 5
+#define AIPS_PACRD_SP6_MASK 0x40u
+#define AIPS_PACRD_SP6_SHIFT 6
+#define AIPS_PACRD_TP5_MASK 0x100u
+#define AIPS_PACRD_TP5_SHIFT 8
+#define AIPS_PACRD_WP5_MASK 0x200u
+#define AIPS_PACRD_WP5_SHIFT 9
+#define AIPS_PACRD_SP5_MASK 0x400u
+#define AIPS_PACRD_SP5_SHIFT 10
+#define AIPS_PACRD_TP4_MASK 0x1000u
+#define AIPS_PACRD_TP4_SHIFT 12
+#define AIPS_PACRD_WP4_MASK 0x2000u
+#define AIPS_PACRD_WP4_SHIFT 13
+#define AIPS_PACRD_SP4_MASK 0x4000u
+#define AIPS_PACRD_SP4_SHIFT 14
+#define AIPS_PACRD_TP3_MASK 0x10000u
+#define AIPS_PACRD_TP3_SHIFT 16
+#define AIPS_PACRD_WP3_MASK 0x20000u
+#define AIPS_PACRD_WP3_SHIFT 17
+#define AIPS_PACRD_SP3_MASK 0x40000u
+#define AIPS_PACRD_SP3_SHIFT 18
+#define AIPS_PACRD_TP2_MASK 0x100000u
+#define AIPS_PACRD_TP2_SHIFT 20
+#define AIPS_PACRD_WP2_MASK 0x200000u
+#define AIPS_PACRD_WP2_SHIFT 21
+#define AIPS_PACRD_SP2_MASK 0x400000u
+#define AIPS_PACRD_SP2_SHIFT 22
+#define AIPS_PACRD_TP1_MASK 0x1000000u
+#define AIPS_PACRD_TP1_SHIFT 24
+#define AIPS_PACRD_WP1_MASK 0x2000000u
+#define AIPS_PACRD_WP1_SHIFT 25
+#define AIPS_PACRD_SP1_MASK 0x4000000u
+#define AIPS_PACRD_SP1_SHIFT 26
+#define AIPS_PACRD_TP0_MASK 0x10000000u
+#define AIPS_PACRD_TP0_SHIFT 28
+#define AIPS_PACRD_WP0_MASK 0x20000000u
+#define AIPS_PACRD_WP0_SHIFT 29
+#define AIPS_PACRD_SP0_MASK 0x40000000u
+#define AIPS_PACRD_SP0_SHIFT 30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK 0x1u
+#define AIPS_PACRE_TP7_SHIFT 0
+#define AIPS_PACRE_WP7_MASK 0x2u
+#define AIPS_PACRE_WP7_SHIFT 1
+#define AIPS_PACRE_SP7_MASK 0x4u
+#define AIPS_PACRE_SP7_SHIFT 2
+#define AIPS_PACRE_TP6_MASK 0x10u
+#define AIPS_PACRE_TP6_SHIFT 4
+#define AIPS_PACRE_WP6_MASK 0x20u
+#define AIPS_PACRE_WP6_SHIFT 5
+#define AIPS_PACRE_SP6_MASK 0x40u
+#define AIPS_PACRE_SP6_SHIFT 6
+#define AIPS_PACRE_TP5_MASK 0x100u
+#define AIPS_PACRE_TP5_SHIFT 8
+#define AIPS_PACRE_WP5_MASK 0x200u
+#define AIPS_PACRE_WP5_SHIFT 9
+#define AIPS_PACRE_SP5_MASK 0x400u
+#define AIPS_PACRE_SP5_SHIFT 10
+#define AIPS_PACRE_TP4_MASK 0x1000u
+#define AIPS_PACRE_TP4_SHIFT 12
+#define AIPS_PACRE_WP4_MASK 0x2000u
+#define AIPS_PACRE_WP4_SHIFT 13
+#define AIPS_PACRE_SP4_MASK 0x4000u
+#define AIPS_PACRE_SP4_SHIFT 14
+#define AIPS_PACRE_TP3_MASK 0x10000u
+#define AIPS_PACRE_TP3_SHIFT 16
+#define AIPS_PACRE_WP3_MASK 0x20000u
+#define AIPS_PACRE_WP3_SHIFT 17
+#define AIPS_PACRE_SP3_MASK 0x40000u
+#define AIPS_PACRE_SP3_SHIFT 18
+#define AIPS_PACRE_TP2_MASK 0x100000u
+#define AIPS_PACRE_TP2_SHIFT 20
+#define AIPS_PACRE_WP2_MASK 0x200000u
+#define AIPS_PACRE_WP2_SHIFT 21
+#define AIPS_PACRE_SP2_MASK 0x400000u
+#define AIPS_PACRE_SP2_SHIFT 22
+#define AIPS_PACRE_TP1_MASK 0x1000000u
+#define AIPS_PACRE_TP1_SHIFT 24
+#define AIPS_PACRE_WP1_MASK 0x2000000u
+#define AIPS_PACRE_WP1_SHIFT 25
+#define AIPS_PACRE_SP1_MASK 0x4000000u
+#define AIPS_PACRE_SP1_SHIFT 26
+#define AIPS_PACRE_TP0_MASK 0x10000000u
+#define AIPS_PACRE_TP0_SHIFT 28
+#define AIPS_PACRE_WP0_MASK 0x20000000u
+#define AIPS_PACRE_WP0_SHIFT 29
+#define AIPS_PACRE_SP0_MASK 0x40000000u
+#define AIPS_PACRE_SP0_SHIFT 30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK 0x1u
+#define AIPS_PACRF_TP7_SHIFT 0
+#define AIPS_PACRF_WP7_MASK 0x2u
+#define AIPS_PACRF_WP7_SHIFT 1
+#define AIPS_PACRF_SP7_MASK 0x4u
+#define AIPS_PACRF_SP7_SHIFT 2
+#define AIPS_PACRF_TP6_MASK 0x10u
+#define AIPS_PACRF_TP6_SHIFT 4
+#define AIPS_PACRF_WP6_MASK 0x20u
+#define AIPS_PACRF_WP6_SHIFT 5
+#define AIPS_PACRF_SP6_MASK 0x40u
+#define AIPS_PACRF_SP6_SHIFT 6
+#define AIPS_PACRF_TP5_MASK 0x100u
+#define AIPS_PACRF_TP5_SHIFT 8
+#define AIPS_PACRF_WP5_MASK 0x200u
+#define AIPS_PACRF_WP5_SHIFT 9
+#define AIPS_PACRF_SP5_MASK 0x400u
+#define AIPS_PACRF_SP5_SHIFT 10
+#define AIPS_PACRF_TP4_MASK 0x1000u
+#define AIPS_PACRF_TP4_SHIFT 12
+#define AIPS_PACRF_WP4_MASK 0x2000u
+#define AIPS_PACRF_WP4_SHIFT 13
+#define AIPS_PACRF_SP4_MASK 0x4000u
+#define AIPS_PACRF_SP4_SHIFT 14
+#define AIPS_PACRF_TP3_MASK 0x10000u
+#define AIPS_PACRF_TP3_SHIFT 16
+#define AIPS_PACRF_WP3_MASK 0x20000u
+#define AIPS_PACRF_WP3_SHIFT 17
+#define AIPS_PACRF_SP3_MASK 0x40000u
+#define AIPS_PACRF_SP3_SHIFT 18
+#define AIPS_PACRF_TP2_MASK 0x100000u
+#define AIPS_PACRF_TP2_SHIFT 20
+#define AIPS_PACRF_WP2_MASK 0x200000u
+#define AIPS_PACRF_WP2_SHIFT 21
+#define AIPS_PACRF_SP2_MASK 0x400000u
+#define AIPS_PACRF_SP2_SHIFT 22
+#define AIPS_PACRF_TP1_MASK 0x1000000u
+#define AIPS_PACRF_TP1_SHIFT 24
+#define AIPS_PACRF_WP1_MASK 0x2000000u
+#define AIPS_PACRF_WP1_SHIFT 25
+#define AIPS_PACRF_SP1_MASK 0x4000000u
+#define AIPS_PACRF_SP1_SHIFT 26
+#define AIPS_PACRF_TP0_MASK 0x10000000u
+#define AIPS_PACRF_TP0_SHIFT 28
+#define AIPS_PACRF_WP0_MASK 0x20000000u
+#define AIPS_PACRF_WP0_SHIFT 29
+#define AIPS_PACRF_SP0_MASK 0x40000000u
+#define AIPS_PACRF_SP0_SHIFT 30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK 0x1u
+#define AIPS_PACRG_TP7_SHIFT 0
+#define AIPS_PACRG_WP7_MASK 0x2u
+#define AIPS_PACRG_WP7_SHIFT 1
+#define AIPS_PACRG_SP7_MASK 0x4u
+#define AIPS_PACRG_SP7_SHIFT 2
+#define AIPS_PACRG_TP6_MASK 0x10u
+#define AIPS_PACRG_TP6_SHIFT 4
+#define AIPS_PACRG_WP6_MASK 0x20u
+#define AIPS_PACRG_WP6_SHIFT 5
+#define AIPS_PACRG_SP6_MASK 0x40u
+#define AIPS_PACRG_SP6_SHIFT 6
+#define AIPS_PACRG_TP5_MASK 0x100u
+#define AIPS_PACRG_TP5_SHIFT 8
+#define AIPS_PACRG_WP5_MASK 0x200u
+#define AIPS_PACRG_WP5_SHIFT 9
+#define AIPS_PACRG_SP5_MASK 0x400u
+#define AIPS_PACRG_SP5_SHIFT 10
+#define AIPS_PACRG_TP4_MASK 0x1000u
+#define AIPS_PACRG_TP4_SHIFT 12
+#define AIPS_PACRG_WP4_MASK 0x2000u
+#define AIPS_PACRG_WP4_SHIFT 13
+#define AIPS_PACRG_SP4_MASK 0x4000u
+#define AIPS_PACRG_SP4_SHIFT 14
+#define AIPS_PACRG_TP3_MASK 0x10000u
+#define AIPS_PACRG_TP3_SHIFT 16
+#define AIPS_PACRG_WP3_MASK 0x20000u
+#define AIPS_PACRG_WP3_SHIFT 17
+#define AIPS_PACRG_SP3_MASK 0x40000u
+#define AIPS_PACRG_SP3_SHIFT 18
+#define AIPS_PACRG_TP2_MASK 0x100000u
+#define AIPS_PACRG_TP2_SHIFT 20
+#define AIPS_PACRG_WP2_MASK 0x200000u
+#define AIPS_PACRG_WP2_SHIFT 21
+#define AIPS_PACRG_SP2_MASK 0x400000u
+#define AIPS_PACRG_SP2_SHIFT 22
+#define AIPS_PACRG_TP1_MASK 0x1000000u
+#define AIPS_PACRG_TP1_SHIFT 24
+#define AIPS_PACRG_WP1_MASK 0x2000000u
+#define AIPS_PACRG_WP1_SHIFT 25
+#define AIPS_PACRG_SP1_MASK 0x4000000u
+#define AIPS_PACRG_SP1_SHIFT 26
+#define AIPS_PACRG_TP0_MASK 0x10000000u
+#define AIPS_PACRG_TP0_SHIFT 28
+#define AIPS_PACRG_WP0_MASK 0x20000000u
+#define AIPS_PACRG_WP0_SHIFT 29
+#define AIPS_PACRG_SP0_MASK 0x40000000u
+#define AIPS_PACRG_SP0_SHIFT 30
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK 0x1u
+#define AIPS_PACRH_TP7_SHIFT 0
+#define AIPS_PACRH_WP7_MASK 0x2u
+#define AIPS_PACRH_WP7_SHIFT 1
+#define AIPS_PACRH_SP7_MASK 0x4u
+#define AIPS_PACRH_SP7_SHIFT 2
+#define AIPS_PACRH_TP6_MASK 0x10u
+#define AIPS_PACRH_TP6_SHIFT 4
+#define AIPS_PACRH_WP6_MASK 0x20u
+#define AIPS_PACRH_WP6_SHIFT 5
+#define AIPS_PACRH_SP6_MASK 0x40u
+#define AIPS_PACRH_SP6_SHIFT 6
+#define AIPS_PACRH_TP5_MASK 0x100u
+#define AIPS_PACRH_TP5_SHIFT 8
+#define AIPS_PACRH_WP5_MASK 0x200u
+#define AIPS_PACRH_WP5_SHIFT 9
+#define AIPS_PACRH_SP5_MASK 0x400u
+#define AIPS_PACRH_SP5_SHIFT 10
+#define AIPS_PACRH_TP4_MASK 0x1000u
+#define AIPS_PACRH_TP4_SHIFT 12
+#define AIPS_PACRH_WP4_MASK 0x2000u
+#define AIPS_PACRH_WP4_SHIFT 13
+#define AIPS_PACRH_SP4_MASK 0x4000u
+#define AIPS_PACRH_SP4_SHIFT 14
+#define AIPS_PACRH_TP3_MASK 0x10000u
+#define AIPS_PACRH_TP3_SHIFT 16
+#define AIPS_PACRH_WP3_MASK 0x20000u
+#define AIPS_PACRH_WP3_SHIFT 17
+#define AIPS_PACRH_SP3_MASK 0x40000u
+#define AIPS_PACRH_SP3_SHIFT 18
+#define AIPS_PACRH_TP2_MASK 0x100000u
+#define AIPS_PACRH_TP2_SHIFT 20
+#define AIPS_PACRH_WP2_MASK 0x200000u
+#define AIPS_PACRH_WP2_SHIFT 21
+#define AIPS_PACRH_SP2_MASK 0x400000u
+#define AIPS_PACRH_SP2_SHIFT 22
+#define AIPS_PACRH_TP1_MASK 0x1000000u
+#define AIPS_PACRH_TP1_SHIFT 24
+#define AIPS_PACRH_WP1_MASK 0x2000000u
+#define AIPS_PACRH_WP1_SHIFT 25
+#define AIPS_PACRH_SP1_MASK 0x4000000u
+#define AIPS_PACRH_SP1_SHIFT 26
+#define AIPS_PACRH_TP0_MASK 0x10000000u
+#define AIPS_PACRH_TP0_SHIFT 28
+#define AIPS_PACRH_WP0_MASK 0x20000000u
+#define AIPS_PACRH_WP0_SHIFT 29
+#define AIPS_PACRH_SP0_MASK 0x40000000u
+#define AIPS_PACRH_SP0_SHIFT 30
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK 0x1u
+#define AIPS_PACRI_TP7_SHIFT 0
+#define AIPS_PACRI_WP7_MASK 0x2u
+#define AIPS_PACRI_WP7_SHIFT 1
+#define AIPS_PACRI_SP7_MASK 0x4u
+#define AIPS_PACRI_SP7_SHIFT 2
+#define AIPS_PACRI_TP6_MASK 0x10u
+#define AIPS_PACRI_TP6_SHIFT 4
+#define AIPS_PACRI_WP6_MASK 0x20u
+#define AIPS_PACRI_WP6_SHIFT 5
+#define AIPS_PACRI_SP6_MASK 0x40u
+#define AIPS_PACRI_SP6_SHIFT 6
+#define AIPS_PACRI_TP5_MASK 0x100u
+#define AIPS_PACRI_TP5_SHIFT 8
+#define AIPS_PACRI_WP5_MASK 0x200u
+#define AIPS_PACRI_WP5_SHIFT 9
+#define AIPS_PACRI_SP5_MASK 0x400u
+#define AIPS_PACRI_SP5_SHIFT 10
+#define AIPS_PACRI_TP4_MASK 0x1000u
+#define AIPS_PACRI_TP4_SHIFT 12
+#define AIPS_PACRI_WP4_MASK 0x2000u
+#define AIPS_PACRI_WP4_SHIFT 13
+#define AIPS_PACRI_SP4_MASK 0x4000u
+#define AIPS_PACRI_SP4_SHIFT 14
+#define AIPS_PACRI_TP3_MASK 0x10000u
+#define AIPS_PACRI_TP3_SHIFT 16
+#define AIPS_PACRI_WP3_MASK 0x20000u
+#define AIPS_PACRI_WP3_SHIFT 17
+#define AIPS_PACRI_SP3_MASK 0x40000u
+#define AIPS_PACRI_SP3_SHIFT 18
+#define AIPS_PACRI_TP2_MASK 0x100000u
+#define AIPS_PACRI_TP2_SHIFT 20
+#define AIPS_PACRI_WP2_MASK 0x200000u
+#define AIPS_PACRI_WP2_SHIFT 21
+#define AIPS_PACRI_SP2_MASK 0x400000u
+#define AIPS_PACRI_SP2_SHIFT 22
+#define AIPS_PACRI_TP1_MASK 0x1000000u
+#define AIPS_PACRI_TP1_SHIFT 24
+#define AIPS_PACRI_WP1_MASK 0x2000000u
+#define AIPS_PACRI_WP1_SHIFT 25
+#define AIPS_PACRI_SP1_MASK 0x4000000u
+#define AIPS_PACRI_SP1_SHIFT 26
+#define AIPS_PACRI_TP0_MASK 0x10000000u
+#define AIPS_PACRI_TP0_SHIFT 28
+#define AIPS_PACRI_WP0_MASK 0x20000000u
+#define AIPS_PACRI_WP0_SHIFT 29
+#define AIPS_PACRI_SP0_MASK 0x40000000u
+#define AIPS_PACRI_SP0_SHIFT 30
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK 0x1u
+#define AIPS_PACRJ_TP7_SHIFT 0
+#define AIPS_PACRJ_WP7_MASK 0x2u
+#define AIPS_PACRJ_WP7_SHIFT 1
+#define AIPS_PACRJ_SP7_MASK 0x4u
+#define AIPS_PACRJ_SP7_SHIFT 2
+#define AIPS_PACRJ_TP6_MASK 0x10u
+#define AIPS_PACRJ_TP6_SHIFT 4
+#define AIPS_PACRJ_WP6_MASK 0x20u
+#define AIPS_PACRJ_WP6_SHIFT 5
+#define AIPS_PACRJ_SP6_MASK 0x40u
+#define AIPS_PACRJ_SP6_SHIFT 6
+#define AIPS_PACRJ_TP5_MASK 0x100u
+#define AIPS_PACRJ_TP5_SHIFT 8
+#define AIPS_PACRJ_WP5_MASK 0x200u
+#define AIPS_PACRJ_WP5_SHIFT 9
+#define AIPS_PACRJ_SP5_MASK 0x400u
+#define AIPS_PACRJ_SP5_SHIFT 10
+#define AIPS_PACRJ_TP4_MASK 0x1000u
+#define AIPS_PACRJ_TP4_SHIFT 12
+#define AIPS_PACRJ_WP4_MASK 0x2000u
+#define AIPS_PACRJ_WP4_SHIFT 13
+#define AIPS_PACRJ_SP4_MASK 0x4000u
+#define AIPS_PACRJ_SP4_SHIFT 14
+#define AIPS_PACRJ_TP3_MASK 0x10000u
+#define AIPS_PACRJ_TP3_SHIFT 16
+#define AIPS_PACRJ_WP3_MASK 0x20000u
+#define AIPS_PACRJ_WP3_SHIFT 17
+#define AIPS_PACRJ_SP3_MASK 0x40000u
+#define AIPS_PACRJ_SP3_SHIFT 18
+#define AIPS_PACRJ_TP2_MASK 0x100000u
+#define AIPS_PACRJ_TP2_SHIFT 20
+#define AIPS_PACRJ_WP2_MASK 0x200000u
+#define AIPS_PACRJ_WP2_SHIFT 21
+#define AIPS_PACRJ_SP2_MASK 0x400000u
+#define AIPS_PACRJ_SP2_SHIFT 22
+#define AIPS_PACRJ_TP1_MASK 0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT 24
+#define AIPS_PACRJ_WP1_MASK 0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT 25
+#define AIPS_PACRJ_SP1_MASK 0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT 26
+#define AIPS_PACRJ_TP0_MASK 0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT 28
+#define AIPS_PACRJ_WP0_MASK 0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT 29
+#define AIPS_PACRJ_SP0_MASK 0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT 30
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK 0x1u
+#define AIPS_PACRK_TP7_SHIFT 0
+#define AIPS_PACRK_WP7_MASK 0x2u
+#define AIPS_PACRK_WP7_SHIFT 1
+#define AIPS_PACRK_SP7_MASK 0x4u
+#define AIPS_PACRK_SP7_SHIFT 2
+#define AIPS_PACRK_TP6_MASK 0x10u
+#define AIPS_PACRK_TP6_SHIFT 4
+#define AIPS_PACRK_WP6_MASK 0x20u
+#define AIPS_PACRK_WP6_SHIFT 5
+#define AIPS_PACRK_SP6_MASK 0x40u
+#define AIPS_PACRK_SP6_SHIFT 6
+#define AIPS_PACRK_TP5_MASK 0x100u
+#define AIPS_PACRK_TP5_SHIFT 8
+#define AIPS_PACRK_WP5_MASK 0x200u
+#define AIPS_PACRK_WP5_SHIFT 9
+#define AIPS_PACRK_SP5_MASK 0x400u
+#define AIPS_PACRK_SP5_SHIFT 10
+#define AIPS_PACRK_TP4_MASK 0x1000u
+#define AIPS_PACRK_TP4_SHIFT 12
+#define AIPS_PACRK_WP4_MASK 0x2000u
+#define AIPS_PACRK_WP4_SHIFT 13
+#define AIPS_PACRK_SP4_MASK 0x4000u
+#define AIPS_PACRK_SP4_SHIFT 14
+#define AIPS_PACRK_TP3_MASK 0x10000u
+#define AIPS_PACRK_TP3_SHIFT 16
+#define AIPS_PACRK_WP3_MASK 0x20000u
+#define AIPS_PACRK_WP3_SHIFT 17
+#define AIPS_PACRK_SP3_MASK 0x40000u
+#define AIPS_PACRK_SP3_SHIFT 18
+#define AIPS_PACRK_TP2_MASK 0x100000u
+#define AIPS_PACRK_TP2_SHIFT 20
+#define AIPS_PACRK_WP2_MASK 0x200000u
+#define AIPS_PACRK_WP2_SHIFT 21
+#define AIPS_PACRK_SP2_MASK 0x400000u
+#define AIPS_PACRK_SP2_SHIFT 22
+#define AIPS_PACRK_TP1_MASK 0x1000000u
+#define AIPS_PACRK_TP1_SHIFT 24
+#define AIPS_PACRK_WP1_MASK 0x2000000u
+#define AIPS_PACRK_WP1_SHIFT 25
+#define AIPS_PACRK_SP1_MASK 0x4000000u
+#define AIPS_PACRK_SP1_SHIFT 26
+#define AIPS_PACRK_TP0_MASK 0x10000000u
+#define AIPS_PACRK_TP0_SHIFT 28
+#define AIPS_PACRK_WP0_MASK 0x20000000u
+#define AIPS_PACRK_WP0_SHIFT 29
+#define AIPS_PACRK_SP0_MASK 0x40000000u
+#define AIPS_PACRK_SP0_SHIFT 30
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK 0x1u
+#define AIPS_PACRL_TP7_SHIFT 0
+#define AIPS_PACRL_WP7_MASK 0x2u
+#define AIPS_PACRL_WP7_SHIFT 1
+#define AIPS_PACRL_SP7_MASK 0x4u
+#define AIPS_PACRL_SP7_SHIFT 2
+#define AIPS_PACRL_TP6_MASK 0x10u
+#define AIPS_PACRL_TP6_SHIFT 4
+#define AIPS_PACRL_WP6_MASK 0x20u
+#define AIPS_PACRL_WP6_SHIFT 5
+#define AIPS_PACRL_SP6_MASK 0x40u
+#define AIPS_PACRL_SP6_SHIFT 6
+#define AIPS_PACRL_TP5_MASK 0x100u
+#define AIPS_PACRL_TP5_SHIFT 8
+#define AIPS_PACRL_WP5_MASK 0x200u
+#define AIPS_PACRL_WP5_SHIFT 9
+#define AIPS_PACRL_SP5_MASK 0x400u
+#define AIPS_PACRL_SP5_SHIFT 10
+#define AIPS_PACRL_TP4_MASK 0x1000u
+#define AIPS_PACRL_TP4_SHIFT 12
+#define AIPS_PACRL_WP4_MASK 0x2000u
+#define AIPS_PACRL_WP4_SHIFT 13
+#define AIPS_PACRL_SP4_MASK 0x4000u
+#define AIPS_PACRL_SP4_SHIFT 14
+#define AIPS_PACRL_TP3_MASK 0x10000u
+#define AIPS_PACRL_TP3_SHIFT 16
+#define AIPS_PACRL_WP3_MASK 0x20000u
+#define AIPS_PACRL_WP3_SHIFT 17
+#define AIPS_PACRL_SP3_MASK 0x40000u
+#define AIPS_PACRL_SP3_SHIFT 18
+#define AIPS_PACRL_TP2_MASK 0x100000u
+#define AIPS_PACRL_TP2_SHIFT 20
+#define AIPS_PACRL_WP2_MASK 0x200000u
+#define AIPS_PACRL_WP2_SHIFT 21
+#define AIPS_PACRL_SP2_MASK 0x400000u
+#define AIPS_PACRL_SP2_SHIFT 22
+#define AIPS_PACRL_TP1_MASK 0x1000000u
+#define AIPS_PACRL_TP1_SHIFT 24
+#define AIPS_PACRL_WP1_MASK 0x2000000u
+#define AIPS_PACRL_WP1_SHIFT 25
+#define AIPS_PACRL_SP1_MASK 0x4000000u
+#define AIPS_PACRL_SP1_SHIFT 26
+#define AIPS_PACRL_TP0_MASK 0x10000000u
+#define AIPS_PACRL_TP0_SHIFT 28
+#define AIPS_PACRL_WP0_MASK 0x20000000u
+#define AIPS_PACRL_WP0_SHIFT 29
+#define AIPS_PACRL_SP0_MASK 0x40000000u
+#define AIPS_PACRL_SP0_SHIFT 30
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK 0x1u
+#define AIPS_PACRM_TP7_SHIFT 0
+#define AIPS_PACRM_WP7_MASK 0x2u
+#define AIPS_PACRM_WP7_SHIFT 1
+#define AIPS_PACRM_SP7_MASK 0x4u
+#define AIPS_PACRM_SP7_SHIFT 2
+#define AIPS_PACRM_TP6_MASK 0x10u
+#define AIPS_PACRM_TP6_SHIFT 4
+#define AIPS_PACRM_WP6_MASK 0x20u
+#define AIPS_PACRM_WP6_SHIFT 5
+#define AIPS_PACRM_SP6_MASK 0x40u
+#define AIPS_PACRM_SP6_SHIFT 6
+#define AIPS_PACRM_TP5_MASK 0x100u
+#define AIPS_PACRM_TP5_SHIFT 8
+#define AIPS_PACRM_WP5_MASK 0x200u
+#define AIPS_PACRM_WP5_SHIFT 9
+#define AIPS_PACRM_SP5_MASK 0x400u
+#define AIPS_PACRM_SP5_SHIFT 10
+#define AIPS_PACRM_TP4_MASK 0x1000u
+#define AIPS_PACRM_TP4_SHIFT 12
+#define AIPS_PACRM_WP4_MASK 0x2000u
+#define AIPS_PACRM_WP4_SHIFT 13
+#define AIPS_PACRM_SP4_MASK 0x4000u
+#define AIPS_PACRM_SP4_SHIFT 14
+#define AIPS_PACRM_TP3_MASK 0x10000u
+#define AIPS_PACRM_TP3_SHIFT 16
+#define AIPS_PACRM_WP3_MASK 0x20000u
+#define AIPS_PACRM_WP3_SHIFT 17
+#define AIPS_PACRM_SP3_MASK 0x40000u
+#define AIPS_PACRM_SP3_SHIFT 18
+#define AIPS_PACRM_TP2_MASK 0x100000u
+#define AIPS_PACRM_TP2_SHIFT 20
+#define AIPS_PACRM_WP2_MASK 0x200000u
+#define AIPS_PACRM_WP2_SHIFT 21
+#define AIPS_PACRM_SP2_MASK 0x400000u
+#define AIPS_PACRM_SP2_SHIFT 22
+#define AIPS_PACRM_TP1_MASK 0x1000000u
+#define AIPS_PACRM_TP1_SHIFT 24
+#define AIPS_PACRM_WP1_MASK 0x2000000u
+#define AIPS_PACRM_WP1_SHIFT 25
+#define AIPS_PACRM_SP1_MASK 0x4000000u
+#define AIPS_PACRM_SP1_SHIFT 26
+#define AIPS_PACRM_TP0_MASK 0x10000000u
+#define AIPS_PACRM_TP0_SHIFT 28
+#define AIPS_PACRM_WP0_MASK 0x20000000u
+#define AIPS_PACRM_WP0_SHIFT 29
+#define AIPS_PACRM_SP0_MASK 0x40000000u
+#define AIPS_PACRM_SP0_SHIFT 30
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK 0x1u
+#define AIPS_PACRN_TP7_SHIFT 0
+#define AIPS_PACRN_WP7_MASK 0x2u
+#define AIPS_PACRN_WP7_SHIFT 1
+#define AIPS_PACRN_SP7_MASK 0x4u
+#define AIPS_PACRN_SP7_SHIFT 2
+#define AIPS_PACRN_TP6_MASK 0x10u
+#define AIPS_PACRN_TP6_SHIFT 4
+#define AIPS_PACRN_WP6_MASK 0x20u
+#define AIPS_PACRN_WP6_SHIFT 5
+#define AIPS_PACRN_SP6_MASK 0x40u
+#define AIPS_PACRN_SP6_SHIFT 6
+#define AIPS_PACRN_TP5_MASK 0x100u
+#define AIPS_PACRN_TP5_SHIFT 8
+#define AIPS_PACRN_WP5_MASK 0x200u
+#define AIPS_PACRN_WP5_SHIFT 9
+#define AIPS_PACRN_SP5_MASK 0x400u
+#define AIPS_PACRN_SP5_SHIFT 10
+#define AIPS_PACRN_TP4_MASK 0x1000u
+#define AIPS_PACRN_TP4_SHIFT 12
+#define AIPS_PACRN_WP4_MASK 0x2000u
+#define AIPS_PACRN_WP4_SHIFT 13
+#define AIPS_PACRN_SP4_MASK 0x4000u
+#define AIPS_PACRN_SP4_SHIFT 14
+#define AIPS_PACRN_TP3_MASK 0x10000u
+#define AIPS_PACRN_TP3_SHIFT 16
+#define AIPS_PACRN_WP3_MASK 0x20000u
+#define AIPS_PACRN_WP3_SHIFT 17
+#define AIPS_PACRN_SP3_MASK 0x40000u
+#define AIPS_PACRN_SP3_SHIFT 18
+#define AIPS_PACRN_TP2_MASK 0x100000u
+#define AIPS_PACRN_TP2_SHIFT 20
+#define AIPS_PACRN_WP2_MASK 0x200000u
+#define AIPS_PACRN_WP2_SHIFT 21
+#define AIPS_PACRN_SP2_MASK 0x400000u
+#define AIPS_PACRN_SP2_SHIFT 22
+#define AIPS_PACRN_TP1_MASK 0x1000000u
+#define AIPS_PACRN_TP1_SHIFT 24
+#define AIPS_PACRN_WP1_MASK 0x2000000u
+#define AIPS_PACRN_WP1_SHIFT 25
+#define AIPS_PACRN_SP1_MASK 0x4000000u
+#define AIPS_PACRN_SP1_SHIFT 26
+#define AIPS_PACRN_TP0_MASK 0x10000000u
+#define AIPS_PACRN_TP0_SHIFT 28
+#define AIPS_PACRN_WP0_MASK 0x20000000u
+#define AIPS_PACRN_WP0_SHIFT 29
+#define AIPS_PACRN_SP0_MASK 0x40000000u
+#define AIPS_PACRN_SP0_SHIFT 30
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK 0x1u
+#define AIPS_PACRO_TP7_SHIFT 0
+#define AIPS_PACRO_WP7_MASK 0x2u
+#define AIPS_PACRO_WP7_SHIFT 1
+#define AIPS_PACRO_SP7_MASK 0x4u
+#define AIPS_PACRO_SP7_SHIFT 2
+#define AIPS_PACRO_TP6_MASK 0x10u
+#define AIPS_PACRO_TP6_SHIFT 4
+#define AIPS_PACRO_WP6_MASK 0x20u
+#define AIPS_PACRO_WP6_SHIFT 5
+#define AIPS_PACRO_SP6_MASK 0x40u
+#define AIPS_PACRO_SP6_SHIFT 6
+#define AIPS_PACRO_TP5_MASK 0x100u
+#define AIPS_PACRO_TP5_SHIFT 8
+#define AIPS_PACRO_WP5_MASK 0x200u
+#define AIPS_PACRO_WP5_SHIFT 9
+#define AIPS_PACRO_SP5_MASK 0x400u
+#define AIPS_PACRO_SP5_SHIFT 10
+#define AIPS_PACRO_TP4_MASK 0x1000u
+#define AIPS_PACRO_TP4_SHIFT 12
+#define AIPS_PACRO_WP4_MASK 0x2000u
+#define AIPS_PACRO_WP4_SHIFT 13
+#define AIPS_PACRO_SP4_MASK 0x4000u
+#define AIPS_PACRO_SP4_SHIFT 14
+#define AIPS_PACRO_TP3_MASK 0x10000u
+#define AIPS_PACRO_TP3_SHIFT 16
+#define AIPS_PACRO_WP3_MASK 0x20000u
+#define AIPS_PACRO_WP3_SHIFT 17
+#define AIPS_PACRO_SP3_MASK 0x40000u
+#define AIPS_PACRO_SP3_SHIFT 18
+#define AIPS_PACRO_TP2_MASK 0x100000u
+#define AIPS_PACRO_TP2_SHIFT 20
+#define AIPS_PACRO_WP2_MASK 0x200000u
+#define AIPS_PACRO_WP2_SHIFT 21
+#define AIPS_PACRO_SP2_MASK 0x400000u
+#define AIPS_PACRO_SP2_SHIFT 22
+#define AIPS_PACRO_TP1_MASK 0x1000000u
+#define AIPS_PACRO_TP1_SHIFT 24
+#define AIPS_PACRO_WP1_MASK 0x2000000u
+#define AIPS_PACRO_WP1_SHIFT 25
+#define AIPS_PACRO_SP1_MASK 0x4000000u
+#define AIPS_PACRO_SP1_SHIFT 26
+#define AIPS_PACRO_TP0_MASK 0x10000000u
+#define AIPS_PACRO_TP0_SHIFT 28
+#define AIPS_PACRO_WP0_MASK 0x20000000u
+#define AIPS_PACRO_WP0_SHIFT 29
+#define AIPS_PACRO_SP0_MASK 0x40000000u
+#define AIPS_PACRO_SP0_SHIFT 30
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK 0x1u
+#define AIPS_PACRP_TP7_SHIFT 0
+#define AIPS_PACRP_WP7_MASK 0x2u
+#define AIPS_PACRP_WP7_SHIFT 1
+#define AIPS_PACRP_SP7_MASK 0x4u
+#define AIPS_PACRP_SP7_SHIFT 2
+#define AIPS_PACRP_TP6_MASK 0x10u
+#define AIPS_PACRP_TP6_SHIFT 4
+#define AIPS_PACRP_WP6_MASK 0x20u
+#define AIPS_PACRP_WP6_SHIFT 5
+#define AIPS_PACRP_SP6_MASK 0x40u
+#define AIPS_PACRP_SP6_SHIFT 6
+#define AIPS_PACRP_TP5_MASK 0x100u
+#define AIPS_PACRP_TP5_SHIFT 8
+#define AIPS_PACRP_WP5_MASK 0x200u
+#define AIPS_PACRP_WP5_SHIFT 9
+#define AIPS_PACRP_SP5_MASK 0x400u
+#define AIPS_PACRP_SP5_SHIFT 10
+#define AIPS_PACRP_TP4_MASK 0x1000u
+#define AIPS_PACRP_TP4_SHIFT 12
+#define AIPS_PACRP_WP4_MASK 0x2000u
+#define AIPS_PACRP_WP4_SHIFT 13
+#define AIPS_PACRP_SP4_MASK 0x4000u
+#define AIPS_PACRP_SP4_SHIFT 14
+#define AIPS_PACRP_TP3_MASK 0x10000u
+#define AIPS_PACRP_TP3_SHIFT 16
+#define AIPS_PACRP_WP3_MASK 0x20000u
+#define AIPS_PACRP_WP3_SHIFT 17
+#define AIPS_PACRP_SP3_MASK 0x40000u
+#define AIPS_PACRP_SP3_SHIFT 18
+#define AIPS_PACRP_TP2_MASK 0x100000u
+#define AIPS_PACRP_TP2_SHIFT 20
+#define AIPS_PACRP_WP2_MASK 0x200000u
+#define AIPS_PACRP_WP2_SHIFT 21
+#define AIPS_PACRP_SP2_MASK 0x400000u
+#define AIPS_PACRP_SP2_SHIFT 22
+#define AIPS_PACRP_TP1_MASK 0x1000000u
+#define AIPS_PACRP_TP1_SHIFT 24
+#define AIPS_PACRP_WP1_MASK 0x2000000u
+#define AIPS_PACRP_WP1_SHIFT 25
+#define AIPS_PACRP_SP1_MASK 0x4000000u
+#define AIPS_PACRP_SP1_SHIFT 26
+#define AIPS_PACRP_TP0_MASK 0x10000000u
+#define AIPS_PACRP_TP0_SHIFT 28
+#define AIPS_PACRP_WP0_MASK 0x20000000u
+#define AIPS_PACRP_WP0_SHIFT 29
+#define AIPS_PACRP_SP0_MASK 0x40000000u
+#define AIPS_PACRP_SP0_SHIFT 30
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base pointer */
+#define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u)
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS { AIPS0_BASE_PTR, AIPS1_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register instance definitions */
+/* AIPS0 */
+#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR)
+#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR)
+/* AIPS1 */
+#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR)
+#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral AXBS
+ * @{
+ */
+
+/** AXBS - Peripheral register structure */
+typedef struct AXBS_MemMap {
+ struct { /* offset: 0x0, array step: 0x100 */
+ uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+ uint8_t RESERVED_0[12];
+ uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_1[236];
+ } SLAVE[8];
+ uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
+ uint8_t RESERVED_0[252];
+ uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
+ uint8_t RESERVED_1[252];
+ uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
+ uint8_t RESERVED_2[252];
+ uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
+ uint8_t RESERVED_3[252];
+ uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
+ uint8_t RESERVED_4[252];
+ uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
+ uint8_t RESERVED_5[252];
+ uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
+ uint8_t RESERVED_6[252];
+ uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */
+} volatile *AXBS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AXBS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
+ * @{
+ */
+
+
+/* AXBS - Register accessors */
+#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
+#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
+#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
+#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
+#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
+#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
+#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
+#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
+#define AXBS_MGPCR6_REG(base) ((base)->MGPCR6)
+#define AXBS_MGPCR7_REG(base) ((base)->MGPCR7)
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AXBS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK 0x7u
+#define AXBS_PRS_M0_SHIFT 0
+#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR)
+#define CAN_CTRL1_REG(base) ((base)->CTRL1)
+#define CAN_TIMER_REG(base) ((base)->TIMER)
+#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
+#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
+#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
+#define CAN_ECR_REG(base) ((base)->ECR)
+#define CAN_ESR1_REG(base) ((base)->ESR1)
+#define CAN_IMASK2_REG(base) ((base)->IMASK2)
+#define CAN_IMASK1_REG(base) ((base)->IMASK1)
+#define CAN_IFLAG2_REG(base) ((base)->IFLAG2)
+#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
+#define CAN_CTRL2_REG(base) ((base)->CTRL2)
+#define CAN_ESR2_REG(base) ((base)->ESR2)
+#define CAN_CRCR_REG(base) ((base)->CRCR)
+#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
+#define CAN_RXFIR_REG(base) ((base)->RXFIR)
+#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
+#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
+#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
+#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
+#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK 0x7Fu
+#define CAN_MCR_MAXMB_SHIFT 0
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index])
+#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
+#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
+#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
+#define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
+#define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
+#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
+#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
+#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
+#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
+#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
+#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
+#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
+#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
+#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
+#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
+#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
+#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
+#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
+#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
+#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
+#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
+#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
+#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
+#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* DIRECT Bit Fields */
+#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
+#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1)
+#define CMT_CGL1_REG(base) ((base)->CGL1)
+#define CMT_CGH2_REG(base) ((base)->CGH2)
+#define CMT_CGL2_REG(base) ((base)->CGL2)
+#define CMT_OC_REG(base) ((base)->OC)
+#define CMT_MSC_REG(base) ((base)->MSC)
+#define CMT_CMD1_REG(base) ((base)->CMD1)
+#define CMT_CMD2_REG(base) ((base)->CMD2)
+#define CMT_CMD3_REG(base) ((base)->CMD3)
+#define CMT_CMD4_REG(base) ((base)->CMD4)
+#define CMT_PPS_REG(base) ((base)->PPS)
+#define CMT_DMA_REG(base) ((base)->DMA)
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.CRCL)
+#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH)
+#define CRC_CRC_REG(base) ((base)->CRC)
+#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL)
+#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU)
+#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL)
+#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU)
+#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base) ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base) ((base)->CTRL)
+#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK 0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT 0
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<base_DHCSR_Read)
+#define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write)
+#define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR)
+#define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR)
+#define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR)
+
+/*!
+ * @}
+ */ /* end of group CoreDebug_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CoreDebug Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group CoreDebug_Register_Masks */
+
+
+/* CoreDebug - Peripheral instance base addresses */
+/** Peripheral CoreDebug base pointer */
+#define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u)
+/** Array initializer of CoreDebug peripheral base pointers */
+#define CoreDebug_BASE_PTRS { CoreDebug_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- CoreDebug - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros
+ * @{
+ */
+
+
+/* CoreDebug - Register instance definitions */
+/* CoreDebug */
+#define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR)
+#define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR)
+#define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR)
+#define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR)
+#define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group CoreDebug_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CoreDebug_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral DAC
+ * @{
+ */
+
+/** DAC - Peripheral register structure */
+typedef struct DAC_MemMap {
+ struct { /* offset: 0x0, array step: 0x2 */
+ uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} volatile *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA_MASK 0xFFu
+#define DAC_DATL_DATA_SHIFT 0
+#define DAC_DATL_DATA(x) (((uint8_t)(((uint8_t)(x))<CR00)
+#define DDR_CR01_REG(base) ((base)->CR01)
+#define DDR_CR02_REG(base) ((base)->CR02)
+#define DDR_CR03_REG(base) ((base)->CR03)
+#define DDR_CR04_REG(base) ((base)->CR04)
+#define DDR_CR05_REG(base) ((base)->CR05)
+#define DDR_CR06_REG(base) ((base)->CR06)
+#define DDR_CR07_REG(base) ((base)->CR07)
+#define DDR_CR08_REG(base) ((base)->CR08)
+#define DDR_CR09_REG(base) ((base)->CR09)
+#define DDR_CR10_REG(base) ((base)->CR10)
+#define DDR_CR11_REG(base) ((base)->CR11)
+#define DDR_CR12_REG(base) ((base)->CR12)
+#define DDR_CR13_REG(base) ((base)->CR13)
+#define DDR_CR14_REG(base) ((base)->CR14)
+#define DDR_CR15_REG(base) ((base)->CR15)
+#define DDR_CR16_REG(base) ((base)->CR16)
+#define DDR_CR17_REG(base) ((base)->CR17)
+#define DDR_CR18_REG(base) ((base)->CR18)
+#define DDR_CR19_REG(base) ((base)->CR19)
+#define DDR_CR20_REG(base) ((base)->CR20)
+#define DDR_CR21_REG(base) ((base)->CR21)
+#define DDR_CR22_REG(base) ((base)->CR22)
+#define DDR_CR23_REG(base) ((base)->CR23)
+#define DDR_CR24_REG(base) ((base)->CR24)
+#define DDR_CR25_REG(base) ((base)->CR25)
+#define DDR_CR26_REG(base) ((base)->CR26)
+#define DDR_CR27_REG(base) ((base)->CR27)
+#define DDR_CR28_REG(base) ((base)->CR28)
+#define DDR_CR29_REG(base) ((base)->CR29)
+#define DDR_CR30_REG(base) ((base)->CR30)
+#define DDR_CR31_REG(base) ((base)->CR31)
+#define DDR_CR32_REG(base) ((base)->CR32)
+#define DDR_CR33_REG(base) ((base)->CR33)
+#define DDR_CR34_REG(base) ((base)->CR34)
+#define DDR_CR35_REG(base) ((base)->CR35)
+#define DDR_CR36_REG(base) ((base)->CR36)
+#define DDR_CR37_REG(base) ((base)->CR37)
+#define DDR_CR38_REG(base) ((base)->CR38)
+#define DDR_CR39_REG(base) ((base)->CR39)
+#define DDR_CR40_REG(base) ((base)->CR40)
+#define DDR_CR41_REG(base) ((base)->CR41)
+#define DDR_CR42_REG(base) ((base)->CR42)
+#define DDR_CR43_REG(base) ((base)->CR43)
+#define DDR_CR44_REG(base) ((base)->CR44)
+#define DDR_CR45_REG(base) ((base)->CR45)
+#define DDR_CR46_REG(base) ((base)->CR46)
+#define DDR_CR47_REG(base) ((base)->CR47)
+#define DDR_CR48_REG(base) ((base)->CR48)
+#define DDR_CR49_REG(base) ((base)->CR49)
+#define DDR_CR50_REG(base) ((base)->CR50)
+#define DDR_CR51_REG(base) ((base)->CR51)
+#define DDR_CR52_REG(base) ((base)->CR52)
+#define DDR_CR53_REG(base) ((base)->CR53)
+#define DDR_CR54_REG(base) ((base)->CR54)
+#define DDR_CR55_REG(base) ((base)->CR55)
+#define DDR_CR56_REG(base) ((base)->CR56)
+#define DDR_CR57_REG(base) ((base)->CR57)
+#define DDR_CR58_REG(base) ((base)->CR58)
+#define DDR_CR59_REG(base) ((base)->CR59)
+#define DDR_CR60_REG(base) ((base)->CR60)
+#define DDR_CR61_REG(base) ((base)->CR61)
+#define DDR_CR62_REG(base) ((base)->CR62)
+#define DDR_CR63_REG(base) ((base)->CR63)
+#define DDR_RCR_REG(base) ((base)->RCR)
+#define DDR_PAD_CTRL_REG(base) ((base)->PAD_CTRL)
+
+/*!
+ * @}
+ */ /* end of group DDR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DDR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DDR_Register_Masks DDR Register Masks
+ * @{
+ */
+
+/* CR00 Bit Fields */
+#define DDR_CR00_START_MASK 0x1u
+#define DDR_CR00_START_SHIFT 0
+#define DDR_CR00_DDRCLS_MASK 0xF00u
+#define DDR_CR00_DDRCLS_SHIFT 8
+#define DDR_CR00_DDRCLS(x) (((uint32_t)(((uint32_t)(x))<CR)
+#define DMA_ES_REG(base) ((base)->ES)
+#define DMA_ERQ_REG(base) ((base)->ERQ)
+#define DMA_EEI_REG(base) ((base)->EEI)
+#define DMA_CEEI_REG(base) ((base)->CEEI)
+#define DMA_SEEI_REG(base) ((base)->SEEI)
+#define DMA_CERQ_REG(base) ((base)->CERQ)
+#define DMA_SERQ_REG(base) ((base)->SERQ)
+#define DMA_CDNE_REG(base) ((base)->CDNE)
+#define DMA_SSRT_REG(base) ((base)->SSRT)
+#define DMA_CERR_REG(base) ((base)->CERR)
+#define DMA_CINT_REG(base) ((base)->CINT)
+#define DMA_INT_REG(base) ((base)->INT)
+#define DMA_ERR_REG(base) ((base)->ERR)
+#define DMA_HRS_REG(base) ((base)->HRS)
+#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
+#define DMA_DCHPRI19_REG(base) ((base)->DCHPRI19)
+#define DMA_DCHPRI18_REG(base) ((base)->DCHPRI18)
+#define DMA_DCHPRI17_REG(base) ((base)->DCHPRI17)
+#define DMA_DCHPRI16_REG(base) ((base)->DCHPRI16)
+#define DMA_DCHPRI23_REG(base) ((base)->DCHPRI23)
+#define DMA_DCHPRI22_REG(base) ((base)->DCHPRI22)
+#define DMA_DCHPRI21_REG(base) ((base)->DCHPRI21)
+#define DMA_DCHPRI20_REG(base) ((base)->DCHPRI20)
+#define DMA_DCHPRI27_REG(base) ((base)->DCHPRI27)
+#define DMA_DCHPRI26_REG(base) ((base)->DCHPRI26)
+#define DMA_DCHPRI25_REG(base) ((base)->DCHPRI25)
+#define DMA_DCHPRI24_REG(base) ((base)->DCHPRI24)
+#define DMA_DCHPRI31_REG(base) ((base)->DCHPRI31)
+#define DMA_DCHPRI30_REG(base) ((base)->DCHPRI30)
+#define DMA_DCHPRI29_REG(base) ((base)->DCHPRI29)
+#define DMA_DCHPRI28_REG(base) ((base)->DCHPRI28)
+#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_ERGA_MASK 0x8u
+#define DMA_CR_ERGA_SHIFT 3
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_GRP0PRI_MASK 0x300u
+#define DMA_CR_GRP0PRI_SHIFT 8
+#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<CTRL)
+#define DWT_CYCCNT_REG(base) ((base)->CYCCNT)
+#define DWT_CPICNT_REG(base) ((base)->CPICNT)
+#define DWT_EXCCNT_REG(base) ((base)->EXCCNT)
+#define DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT)
+#define DWT_LSUCNT_REG(base) ((base)->LSUCNT)
+#define DWT_FOLDCNT_REG(base) ((base)->FOLDCNT)
+#define DWT_PCSR_REG(base) ((base)->PCSR)
+#define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
+#define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
+#define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION)
+#define DWT_PID4_REG(base) ((base)->PID4)
+#define DWT_PID5_REG(base) ((base)->PID5)
+#define DWT_PID6_REG(base) ((base)->PID6)
+#define DWT_PID7_REG(base) ((base)->PID7)
+#define DWT_PID0_REG(base) ((base)->PID0)
+#define DWT_PID1_REG(base) ((base)->PID1)
+#define DWT_PID2_REG(base) ((base)->PID2)
+#define DWT_PID3_REG(base) ((base)->PID3)
+#define DWT_CID0_REG(base) ((base)->CID0)
+#define DWT_CID1_REG(base) ((base)->CID1)
+#define DWT_CID2_REG(base) ((base)->CID2)
+#define DWT_CID3_REG(base) ((base)->CID3)
+
+/*!
+ * @}
+ */ /* end of group DWT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DWT_Register_Masks DWT Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group DWT_Register_Masks */
+
+
+/* DWT - Peripheral instance base addresses */
+/** Peripheral DWT base pointer */
+#define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u)
+/** Array initializer of DWT peripheral base pointers */
+#define DWT_BASE_PTRS { DWT_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- DWT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros
+ * @{
+ */
+
+
+/* DWT - Register instance definitions */
+/* DWT */
+#define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR)
+#define DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR)
+#define DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR)
+#define DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR)
+#define DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR)
+#define DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR)
+#define DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR)
+#define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR)
+#define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0)
+#define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0)
+#define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0)
+#define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1)
+#define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1)
+#define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1)
+#define DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2)
+#define DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2)
+#define DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2)
+#define DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3)
+#define DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3)
+#define DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3)
+#define DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR)
+#define DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR)
+#define DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR)
+#define DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR)
+#define DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR)
+#define DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR)
+#define DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR)
+#define DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR)
+#define DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR)
+#define DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR)
+#define DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR)
+#define DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR)
+
+/* DWT - Register array accessors */
+#define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index)
+#define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index)
+#define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index)
+
+/*!
+ * @}
+ */ /* end of group DWT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DWT_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral ENET
+ * @{
+ */
+
+/** ENET - Peripheral register structure */
+typedef struct ENET_MemMap {
+ uint8_t RESERVED_0[4];
+ uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
+ uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
+ uint8_t RESERVED_1[4];
+ uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
+ uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
+ uint8_t RESERVED_2[12];
+ uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
+ uint8_t RESERVED_3[24];
+ uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
+ uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
+ uint8_t RESERVED_4[28];
+ uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
+ uint8_t RESERVED_5[28];
+ uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
+ uint8_t RESERVED_6[60];
+ uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
+ uint8_t RESERVED_7[28];
+ uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
+ uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
+ uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
+ uint8_t RESERVED_8[40];
+ uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+ uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+ uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
+ uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
+ uint8_t RESERVED_9[28];
+ uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
+ uint8_t RESERVED_10[56];
+ uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+ uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+ uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+ uint8_t RESERVED_11[4];
+ uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+ uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+ uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+ uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+ uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+ uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+ uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+ uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+ uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
+ uint8_t RESERVED_12[12];
+ uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+ uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+ uint8_t RESERVED_13[56];
+ uint32_t RMON_T_DROP; /**< Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200 */
+ uint32_t RMON_T_PACKETS; /**< RMON Tx packet count (RMON_T_PACKETS), offset: 0x204 */
+ uint32_t RMON_T_BC_PKT; /**< RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208 */
+ uint32_t RMON_T_MC_PKT; /**< RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C */
+ uint32_t RMON_T_CRC_ALIGN; /**< RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210 */
+ uint32_t RMON_T_UNDERSIZE; /**< RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214 */
+ uint32_t RMON_T_OVERSIZE; /**< RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */
+ uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */
+ uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */
+ uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */
+ uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */
+ uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */
+ uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */
+ uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */
+ uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */
+ uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */
+ uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */
+ uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */
+ uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */
+ uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */
+ uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */
+ uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */
+ uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */
+ uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */
+ uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */
+ uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */
+ uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */
+ uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */
+ uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */
+ uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */
+ uint8_t RESERVED_14[12];
+ uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */
+ uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */
+ uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */
+ uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */
+ uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */
+ uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */
+ uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */
+ uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */
+ uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */
+ uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */
+ uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */
+ uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */
+ uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */
+ uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */
+ uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */
+ uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */
+ uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */
+ uint32_t IEEE_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */
+ uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */
+ uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */
+ uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */
+ uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */
+ uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */
+ uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */
+ uint8_t RESERVED_15[284];
+ uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */
+ uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
+ uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
+ uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
+ uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
+ uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
+ uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+ uint8_t RESERVED_16[488];
+ uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
+ struct { /* offset: 0x608, array step: 0x8 */
+ uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+ uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+ } CHANNEL[4];
+} volatile *ENET_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ENET - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
+ * @{
+ */
+
+
+/* ENET - Register accessors */
+#define ENET_EIR_REG(base) ((base)->EIR)
+#define ENET_EIMR_REG(base) ((base)->EIMR)
+#define ENET_RDAR_REG(base) ((base)->RDAR)
+#define ENET_TDAR_REG(base) ((base)->TDAR)
+#define ENET_ECR_REG(base) ((base)->ECR)
+#define ENET_MMFR_REG(base) ((base)->MMFR)
+#define ENET_MSCR_REG(base) ((base)->MSCR)
+#define ENET_MIBC_REG(base) ((base)->MIBC)
+#define ENET_RCR_REG(base) ((base)->RCR)
+#define ENET_TCR_REG(base) ((base)->TCR)
+#define ENET_PALR_REG(base) ((base)->PALR)
+#define ENET_PAUR_REG(base) ((base)->PAUR)
+#define ENET_OPD_REG(base) ((base)->OPD)
+#define ENET_IAUR_REG(base) ((base)->IAUR)
+#define ENET_IALR_REG(base) ((base)->IALR)
+#define ENET_GAUR_REG(base) ((base)->GAUR)
+#define ENET_GALR_REG(base) ((base)->GALR)
+#define ENET_TFWR_REG(base) ((base)->TFWR)
+#define ENET_RDSR_REG(base) ((base)->RDSR)
+#define ENET_TDSR_REG(base) ((base)->TDSR)
+#define ENET_MRBR_REG(base) ((base)->MRBR)
+#define ENET_RSFL_REG(base) ((base)->RSFL)
+#define ENET_RSEM_REG(base) ((base)->RSEM)
+#define ENET_RAEM_REG(base) ((base)->RAEM)
+#define ENET_RAFL_REG(base) ((base)->RAFL)
+#define ENET_TSEM_REG(base) ((base)->TSEM)
+#define ENET_TAEM_REG(base) ((base)->TAEM)
+#define ENET_TAFL_REG(base) ((base)->TAFL)
+#define ENET_TIPG_REG(base) ((base)->TIPG)
+#define ENET_FTRL_REG(base) ((base)->FTRL)
+#define ENET_TACC_REG(base) ((base)->TACC)
+#define ENET_RACC_REG(base) ((base)->RACC)
+#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP)
+#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
+#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
+#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
+#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
+#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
+#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
+#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
+#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
+#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
+#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
+#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
+#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
+#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
+#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
+#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
+#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
+#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
+#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP)
+#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
+#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
+#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
+#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
+#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
+#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
+#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
+#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
+#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE)
+#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
+#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
+#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
+#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
+#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
+#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
+#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
+#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
+#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
+#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
+#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0)
+#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
+#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
+#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
+#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
+#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
+#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
+#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
+#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
+#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
+#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
+#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
+#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
+#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
+#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
+#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
+#define ENET_ATCR_REG(base) ((base)->ATCR)
+#define ENET_ATVR_REG(base) ((base)->ATVR)
+#define ENET_ATOFF_REG(base) ((base)->ATOFF)
+#define ENET_ATPER_REG(base) ((base)->ATPER)
+#define ENET_ATCOR_REG(base) ((base)->ATCOR)
+#define ENET_ATINC_REG(base) ((base)->ATINC)
+#define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
+#define ENET_TGSR_REG(base) ((base)->TGSR)
+#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
+#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/* EIR Bit Fields */
+#define ENET_EIR_TS_TIMER_MASK 0x8000u
+#define ENET_EIR_TS_TIMER_SHIFT 15
+#define ENET_EIR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIR_TS_AVAIL_SHIFT 16
+#define ENET_EIR_WAKEUP_MASK 0x20000u
+#define ENET_EIR_WAKEUP_SHIFT 17
+#define ENET_EIR_PLR_MASK 0x40000u
+#define ENET_EIR_PLR_SHIFT 18
+#define ENET_EIR_UN_MASK 0x80000u
+#define ENET_EIR_UN_SHIFT 19
+#define ENET_EIR_RL_MASK 0x100000u
+#define ENET_EIR_RL_SHIFT 20
+#define ENET_EIR_LC_MASK 0x200000u
+#define ENET_EIR_LC_SHIFT 21
+#define ENET_EIR_EBERR_MASK 0x400000u
+#define ENET_EIR_EBERR_SHIFT 22
+#define ENET_EIR_MII_MASK 0x800000u
+#define ENET_EIR_MII_SHIFT 23
+#define ENET_EIR_RXB_MASK 0x1000000u
+#define ENET_EIR_RXB_SHIFT 24
+#define ENET_EIR_RXF_MASK 0x2000000u
+#define ENET_EIR_RXF_SHIFT 25
+#define ENET_EIR_TXB_MASK 0x4000000u
+#define ENET_EIR_TXB_SHIFT 26
+#define ENET_EIR_TXF_MASK 0x8000000u
+#define ENET_EIR_TXF_SHIFT 27
+#define ENET_EIR_GRA_MASK 0x10000000u
+#define ENET_EIR_GRA_SHIFT 28
+#define ENET_EIR_BABT_MASK 0x20000000u
+#define ENET_EIR_BABT_SHIFT 29
+#define ENET_EIR_BABR_MASK 0x40000000u
+#define ENET_EIR_BABR_SHIFT 30
+/* EIMR Bit Fields */
+#define ENET_EIMR_TS_TIMER_MASK 0x8000u
+#define ENET_EIMR_TS_TIMER_SHIFT 15
+#define ENET_EIMR_TS_AVAIL_MASK 0x10000u
+#define ENET_EIMR_TS_AVAIL_SHIFT 16
+#define ENET_EIMR_WAKEUP_MASK 0x20000u
+#define ENET_EIMR_WAKEUP_SHIFT 17
+#define ENET_EIMR_PLR_MASK 0x40000u
+#define ENET_EIMR_PLR_SHIFT 18
+#define ENET_EIMR_UN_MASK 0x80000u
+#define ENET_EIMR_UN_SHIFT 19
+#define ENET_EIMR_RL_MASK 0x100000u
+#define ENET_EIMR_RL_SHIFT 20
+#define ENET_EIMR_LC_MASK 0x200000u
+#define ENET_EIMR_LC_SHIFT 21
+#define ENET_EIMR_EBERR_MASK 0x400000u
+#define ENET_EIMR_EBERR_SHIFT 22
+#define ENET_EIMR_MII_MASK 0x800000u
+#define ENET_EIMR_MII_SHIFT 23
+#define ENET_EIMR_RXB_MASK 0x1000000u
+#define ENET_EIMR_RXB_SHIFT 24
+#define ENET_EIMR_RXF_MASK 0x2000000u
+#define ENET_EIMR_RXF_SHIFT 25
+#define ENET_EIMR_TXB_MASK 0x4000000u
+#define ENET_EIMR_TXB_SHIFT 26
+#define ENET_EIMR_TXF_MASK 0x8000000u
+#define ENET_EIMR_TXF_SHIFT 27
+#define ENET_EIMR_GRA_MASK 0x10000000u
+#define ENET_EIMR_GRA_SHIFT 28
+#define ENET_EIMR_BABT_MASK 0x20000000u
+#define ENET_EIMR_BABT_SHIFT 29
+#define ENET_EIMR_BABR_MASK 0x40000000u
+#define ENET_EIMR_BABR_SHIFT 30
+/* RDAR Bit Fields */
+#define ENET_RDAR_RDAR_MASK 0x1000000u
+#define ENET_RDAR_RDAR_SHIFT 24
+/* TDAR Bit Fields */
+#define ENET_TDAR_TDAR_MASK 0x1000000u
+#define ENET_TDAR_TDAR_SHIFT 24
+/* ECR Bit Fields */
+#define ENET_ECR_RESET_MASK 0x1u
+#define ENET_ECR_RESET_SHIFT 0
+#define ENET_ECR_ETHEREN_MASK 0x2u
+#define ENET_ECR_ETHEREN_SHIFT 1
+#define ENET_ECR_MAGICEN_MASK 0x4u
+#define ENET_ECR_MAGICEN_SHIFT 2
+#define ENET_ECR_SLEEP_MASK 0x8u
+#define ENET_ECR_SLEEP_SHIFT 3
+#define ENET_ECR_EN1588_MASK 0x10u
+#define ENET_ECR_EN1588_SHIFT 4
+#define ENET_ECR_DBGEN_MASK 0x40u
+#define ENET_ECR_DBGEN_SHIFT 6
+#define ENET_ECR_STOPEN_MASK 0x80u
+#define ENET_ECR_STOPEN_SHIFT 7
+#define ENET_ECR_DBSWP_MASK 0x100u
+#define ENET_ECR_DBSWP_SHIFT 8
+/* MMFR Bit Fields */
+#define ENET_MMFR_DATA_MASK 0xFFFFu
+#define ENET_MMFR_DATA_SHIFT 0
+#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<RDP)
+#define ETB_STS_REG(base) ((base)->STS)
+#define ETB_RRD_REG(base) ((base)->RRD)
+#define ETB_RRP_REG(base) ((base)->RRP)
+#define ETB_RWP_REG(base) ((base)->RWP)
+#define ETB_TRG_REG(base) ((base)->TRG)
+#define ETB_CTL_REG(base) ((base)->CTL)
+#define ETB_RWD_REG(base) ((base)->RWD)
+#define ETB_FFSR_REG(base) ((base)->FFSR)
+#define ETB_FFCR_REG(base) ((base)->FFCR)
+#define ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0)
+#define ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK)
+#define ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN)
+#define ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0)
+#define ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
+#define ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1)
+#define ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
+#define ETB_ITCTRL_REG(base) ((base)->ITCTRL)
+#define ETB_CLAIMSET_REG(base) ((base)->CLAIMSET)
+#define ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
+#define ETB_LAR_REG(base) ((base)->LAR)
+#define ETB_LSR_REG(base) ((base)->LSR)
+#define ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
+#define ETB_DEVID_REG(base) ((base)->DEVID)
+#define ETB_DEVTYPE_REG(base) ((base)->DEVTYPE)
+#define ETB_PIDR4_REG(base) ((base)->PIDR4)
+#define ETB_PIDR5_REG(base) ((base)->PIDR5)
+#define ETB_PIDR6_REG(base) ((base)->PIDR6)
+#define ETB_PIDR7_REG(base) ((base)->PIDR7)
+#define ETB_PIDR0_REG(base) ((base)->PIDR0)
+#define ETB_PIDR1_REG(base) ((base)->PIDR1)
+#define ETB_PIDR2_REG(base) ((base)->PIDR2)
+#define ETB_PIDR3_REG(base) ((base)->PIDR3)
+#define ETB_CIDR0_REG(base) ((base)->CIDR0)
+#define ETB_CIDR1_REG(base) ((base)->CIDR1)
+#define ETB_CIDR2_REG(base) ((base)->CIDR2)
+#define ETB_CIDR3_REG(base) ((base)->CIDR3)
+
+/*!
+ * @}
+ */ /* end of group ETB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ETB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETB_Register_Masks ETB Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group ETB_Register_Masks */
+
+
+/* ETB - Peripheral instance base addresses */
+/** Peripheral ETB base pointer */
+#define ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u)
+/** Array initializer of ETB peripheral base pointers */
+#define ETB_BASE_PTRS { ETB_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- ETB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros
+ * @{
+ */
+
+
+/* ETB - Register instance definitions */
+/* ETB */
+#define ETB_RDP ETB_RDP_REG(ETB_BASE_PTR)
+#define ETB_STS ETB_STS_REG(ETB_BASE_PTR)
+#define ETB_RRD ETB_RRD_REG(ETB_BASE_PTR)
+#define ETB_RRP ETB_RRP_REG(ETB_BASE_PTR)
+#define ETB_RWP ETB_RWP_REG(ETB_BASE_PTR)
+#define ETB_TRG ETB_TRG_REG(ETB_BASE_PTR)
+#define ETB_CTL ETB_CTL_REG(ETB_BASE_PTR)
+#define ETB_RWD ETB_RWD_REG(ETB_BASE_PTR)
+#define ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR)
+#define ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR)
+#define ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR)
+#define ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR)
+#define ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR)
+#define ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR)
+#define ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR)
+#define ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR)
+#define ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR)
+#define ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR)
+#define ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR)
+#define ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR)
+#define ETB_LAR ETB_LAR_REG(ETB_BASE_PTR)
+#define ETB_LSR ETB_LSR_REG(ETB_BASE_PTR)
+#define ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR)
+#define ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR)
+#define ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR)
+#define ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR)
+#define ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR)
+#define ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR)
+#define ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR)
+#define ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR)
+#define ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR)
+#define ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR)
+#define ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR)
+#define ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR)
+#define ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR)
+#define ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR)
+#define ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group ETB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ETB_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- ETF
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETF_Peripheral ETF
+ * @{
+ */
+
+/** ETF - Peripheral register structure */
+typedef struct ETF_MemMap {
+ uint32_t FCR; /**< Funnel Control Register, offset: 0x0 */
+ uint32_t PCR; /**< Priority Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[3812];
+ uint32_t ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */
+ uint32_t ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */
+ uint32_t ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */
+ uint32_t ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */
+ uint8_t RESERVED_1[4];
+ uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_2[156];
+ uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
+ uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_3[8];
+ uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
+ uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
+ uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */
+ uint8_t RESERVED_4[12];
+ uint32_t DEVID; /**< Device ID Register, offset: 0xFC8 */
+ uint32_t DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */
+ uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */
+ uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */
+ uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */
+ uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */
+ uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */
+ uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */
+ uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */
+ uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */
+ uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */
+ uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */
+ uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */
+ uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */
+} volatile *ETF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ETF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros
+ * @{
+ */
+
+
+/* ETF - Register accessors */
+#define ETF_FCR_REG(base) ((base)->FCR)
+#define ETF_PCR_REG(base) ((base)->PCR)
+#define ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0)
+#define ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
+#define ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1)
+#define ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
+#define ETF_ITCTRL_REG(base) ((base)->ITCTRL)
+#define ETF_CLAIMSET_REG(base) ((base)->CLAIMSET)
+#define ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
+#define ETF_LAR_REG(base) ((base)->LAR)
+#define ETF_LSR_REG(base) ((base)->LSR)
+#define ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
+#define ETF_DEVID_REG(base) ((base)->DEVID)
+#define ETF_DEVTYPE_REG(base) ((base)->DEVTYPE)
+#define ETF_PIDR4_REG(base) ((base)->PIDR4)
+#define ETF_PIDR5_REG(base) ((base)->PIDR5)
+#define ETF_PIDR6_REG(base) ((base)->PIDR6)
+#define ETF_PIDR7_REG(base) ((base)->PIDR7)
+#define ETF_PIDR0_REG(base) ((base)->PIDR0)
+#define ETF_PIDR1_REG(base) ((base)->PIDR1)
+#define ETF_PIDR2_REG(base) ((base)->PIDR2)
+#define ETF_PIDR3_REG(base) ((base)->PIDR3)
+#define ETF_CIDR0_REG(base) ((base)->CIDR0)
+#define ETF_CIDR1_REG(base) ((base)->CIDR1)
+#define ETF_CIDR2_REG(base) ((base)->CIDR2)
+#define ETF_CIDR3_REG(base) ((base)->CIDR3)
+
+/*!
+ * @}
+ */ /* end of group ETF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ETF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETF_Register_Masks ETF Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group ETF_Register_Masks */
+
+
+/* ETF - Peripheral instance base addresses */
+/** Peripheral ETF base pointer */
+#define ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u)
+/** Array initializer of ETF peripheral base pointers */
+#define ETF_BASE_PTRS { ETF_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- ETF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros
+ * @{
+ */
+
+
+/* ETF - Register instance definitions */
+/* ETF */
+#define ETF_FCR ETF_FCR_REG(ETF_BASE_PTR)
+#define ETF_PCR ETF_PCR_REG(ETF_BASE_PTR)
+#define ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR)
+#define ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR)
+#define ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR)
+#define ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR)
+#define ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR)
+#define ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR)
+#define ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR)
+#define ETF_LAR ETF_LAR_REG(ETF_BASE_PTR)
+#define ETF_LSR ETF_LSR_REG(ETF_BASE_PTR)
+#define ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR)
+#define ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR)
+#define ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR)
+#define ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR)
+#define ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR)
+#define ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR)
+#define ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR)
+#define ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR)
+#define ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR)
+#define ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR)
+#define ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR)
+#define ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR)
+#define ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR)
+#define ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR)
+#define ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group ETF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ETF_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- ETM
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Peripheral ETM
+ * @{
+ */
+
+/** ETM - Peripheral register structure */
+typedef struct ETM_MemMap {
+ uint32_t CR; /**< Main Control Register, offset: 0x0 */
+ uint32_t CCR; /**< Configuration Code Register, offset: 0x4 */
+ uint32_t TRIGGER; /**< Trigger Event Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ uint32_t SR; /**< ETM Status Register, offset: 0x10 */
+ uint32_t SCR; /**< System Configuration Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ uint32_t EEVR; /**< Trace Enable Event Register, offset: 0x20 */
+ uint32_t TECR1; /**< Trace Enable Control 1 Register, offset: 0x24 */
+ uint32_t FFLR; /**< FIFOFULL Level Register, offset: 0x28 */
+ uint8_t RESERVED_2[276];
+ uint32_t CNTRLDVR1; /**< Free-running counter reload value, offset: 0x140 */
+ uint8_t RESERVED_3[156];
+ uint32_t SYNCFR; /**< Synchronization Frequency Register, offset: 0x1E0 */
+ uint32_t IDR; /**< ID Register, offset: 0x1E4 */
+ uint32_t CCER; /**< Configuration Code Extension Register, offset: 0x1E8 */
+ uint8_t RESERVED_4[4];
+ uint32_t TESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register, offset: 0x1F0 */
+ uint8_t RESERVED_5[4];
+ uint32_t TSEVR; /**< Timestamp Event Register, offset: 0x1F8 */
+ uint8_t RESERVED_6[4];
+ uint32_t TRACEIDR; /**< CoreSight Trace ID Register, offset: 0x200 */
+ uint8_t RESERVED_7[4];
+ uint32_t IDR2; /**< ETM ID Register 2, offset: 0x208 */
+ uint8_t RESERVED_8[264];
+ uint32_t PDSR; /**< Device Power-Down Status Register, offset: 0x314 */
+ uint8_t RESERVED_9[3016];
+ uint32_t ITMISCIN; /**< Integration Test Miscelaneous Inputs Register, offset: 0xEE0 */
+ uint8_t RESERVED_10[4];
+ uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register, offset: 0xEE8 */
+ uint8_t RESERVED_11[4];
+ uint32_t ITATBCTR2; /**< ETM Integration Test ATB Control 2 Register, offset: 0xEF0 */
+ uint8_t RESERVED_12[4];
+ uint32_t ITATBCTR0; /**< ETM Integration Test ATB Control 0 Register, offset: 0xEF8 */
+ uint8_t RESERVED_13[4];
+ uint32_t ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_14[156];
+ uint32_t CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */
+ uint32_t CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_15[8];
+ uint32_t LAR; /**< Lock Access Register, offset: 0xFB0 */
+ uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */
+ uint32_t AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */
+ uint8_t RESERVED_16[16];
+ uint32_t DEVTYPE; /**< CoreSight Device Type Register, offset: 0xFCC */
+ uint32_t PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */
+ uint32_t PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */
+ uint32_t PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */
+ uint32_t PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */
+ uint32_t PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */
+ uint32_t PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */
+ uint32_t PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */
+ uint32_t PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */
+ uint32_t CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */
+ uint32_t CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */
+ uint32_t CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */
+ uint32_t CIDR3; /**< Component Identification Register 3, offset: 0xFFC */
+} volatile *ETM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ETM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros
+ * @{
+ */
+
+
+/* ETM - Register accessors */
+#define ETM_CR_REG(base) ((base)->CR)
+#define ETM_CCR_REG(base) ((base)->CCR)
+#define ETM_TRIGGER_REG(base) ((base)->TRIGGER)
+#define ETM_SR_REG(base) ((base)->SR)
+#define ETM_SCR_REG(base) ((base)->SCR)
+#define ETM_EEVR_REG(base) ((base)->EEVR)
+#define ETM_TECR1_REG(base) ((base)->TECR1)
+#define ETM_FFLR_REG(base) ((base)->FFLR)
+#define ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1)
+#define ETM_SYNCFR_REG(base) ((base)->SYNCFR)
+#define ETM_IDR_REG(base) ((base)->IDR)
+#define ETM_CCER_REG(base) ((base)->CCER)
+#define ETM_TESSEICR_REG(base) ((base)->TESSEICR)
+#define ETM_TSEVR_REG(base) ((base)->TSEVR)
+#define ETM_TRACEIDR_REG(base) ((base)->TRACEIDR)
+#define ETM_IDR2_REG(base) ((base)->IDR2)
+#define ETM_PDSR_REG(base) ((base)->PDSR)
+#define ETM_ITMISCIN_REG(base) ((base)->ITMISCIN)
+#define ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT)
+#define ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
+#define ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
+#define ETM_ITCTRL_REG(base) ((base)->ITCTRL)
+#define ETM_CLAIMSET_REG(base) ((base)->CLAIMSET)
+#define ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
+#define ETM_LAR_REG(base) ((base)->LAR)
+#define ETM_LSR_REG(base) ((base)->LSR)
+#define ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS)
+#define ETM_DEVTYPE_REG(base) ((base)->DEVTYPE)
+#define ETM_PIDR4_REG(base) ((base)->PIDR4)
+#define ETM_PIDR5_REG(base) ((base)->PIDR5)
+#define ETM_PIDR6_REG(base) ((base)->PIDR6)
+#define ETM_PIDR7_REG(base) ((base)->PIDR7)
+#define ETM_PIDR0_REG(base) ((base)->PIDR0)
+#define ETM_PIDR1_REG(base) ((base)->PIDR1)
+#define ETM_PIDR2_REG(base) ((base)->PIDR2)
+#define ETM_PIDR3_REG(base) ((base)->PIDR3)
+#define ETM_CIDR0_REG(base) ((base)->CIDR0)
+#define ETM_CIDR1_REG(base) ((base)->CIDR1)
+#define ETM_CIDR2_REG(base) ((base)->CIDR2)
+#define ETM_CIDR3_REG(base) ((base)->CIDR3)
+
+/*!
+ * @}
+ */ /* end of group ETM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ETM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Register_Masks ETM Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group ETM_Register_Masks */
+
+
+/* ETM - Peripheral instance base addresses */
+/** Peripheral ETM base pointer */
+#define ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u)
+/** Array initializer of ETM peripheral base pointers */
+#define ETM_BASE_PTRS { ETM_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- ETM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros
+ * @{
+ */
+
+
+/* ETM - Register instance definitions */
+/* ETM */
+#define ETMCR ETM_CR_REG(ETM_BASE_PTR)
+#define ETMCCR ETM_CCR_REG(ETM_BASE_PTR)
+#define ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR)
+#define ETMSR ETM_SR_REG(ETM_BASE_PTR)
+#define ETMSCR ETM_SCR_REG(ETM_BASE_PTR)
+#define ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR)
+#define ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR)
+#define ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR)
+#define ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR)
+#define ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR)
+#define ETMIDR ETM_IDR_REG(ETM_BASE_PTR)
+#define ETMCCER ETM_CCER_REG(ETM_BASE_PTR)
+#define ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR)
+#define ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR)
+#define ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR)
+#define ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR)
+#define ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR)
+#define ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR)
+#define ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR)
+#define ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR)
+#define ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR)
+#define ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR)
+#define ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR)
+#define ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR)
+#define ETMLAR ETM_LAR_REG(ETM_BASE_PTR)
+#define ETMLSR ETM_LSR_REG(ETM_BASE_PTR)
+#define ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR)
+#define ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR)
+#define ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR)
+#define ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR)
+#define ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR)
+#define ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR)
+#define ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR)
+#define ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR)
+#define ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR)
+#define ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR)
+#define ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR)
+#define ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR)
+#define ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR)
+#define ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group ETM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ETM_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral EWM
+ * @{
+ */
+
+/** EWM - Peripheral register structure */
+typedef struct EWM_MemMap {
+ uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ uint8_t SERV; /**< Service Register, offset: 0x1 */
+ uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} volatile *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base) ((base)->CTRL)
+#define EWM_SERV_REG(base) ((base)->SERV)
+#define EWM_CMPL_REG(base) ((base)->CMPL)
+#define EWM_CMPH_REG(base) ((base)->CMPH)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR)
+#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK 0xFFFF0000u
+#define FB_CSAR_BA_SHIFT 16
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR)
+#define FMC_PFB01CR_REG(base) ((base)->PFB01CR)
+#define FMC_PFB23CR_REG(base) ((base)->PFB23CR)
+#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2])
+#define FMC_DATA_UM_REG(base,index,index2) ((base)->SET[index][index2].DATA_UM)
+#define FMC_DATA_MU_REG(base,index,index2) ((base)->SET[index][index2].DATA_MU)
+#define FMC_DATA_ML_REG(base,index,index2) ((base)->SET[index][index2].DATA_ML)
+#define FMC_DATA_LM_REG(base,index,index2) ((base)->SET[index][index2].DATA_LM)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<CTRL)
+#define FPB_REMAP_REG(base) ((base)->REMAP)
+#define FPB_COMP_REG(base,index) ((base)->COMP[index])
+#define FPB_PID4_REG(base) ((base)->PID4)
+#define FPB_PID5_REG(base) ((base)->PID5)
+#define FPB_PID6_REG(base) ((base)->PID6)
+#define FPB_PID7_REG(base) ((base)->PID7)
+#define FPB_PID0_REG(base) ((base)->PID0)
+#define FPB_PID1_REG(base) ((base)->PID1)
+#define FPB_PID2_REG(base) ((base)->PID2)
+#define FPB_PID3_REG(base) ((base)->PID3)
+#define FPB_CID0_REG(base) ((base)->CID0)
+#define FPB_CID1_REG(base) ((base)->CID1)
+#define FPB_CID2_REG(base) ((base)->CID2)
+#define FPB_CID3_REG(base) ((base)->CID3)
+
+/*!
+ * @}
+ */ /* end of group FPB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FPB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FPB_Register_Masks FPB Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group FPB_Register_Masks */
+
+
+/* FPB - Peripheral instance base addresses */
+/** Peripheral FPB base pointer */
+#define FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u)
+/** Array initializer of FPB peripheral base pointers */
+#define FPB_BASE_PTRS { FPB_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- FPB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros
+ * @{
+ */
+
+
+/* FPB - Register instance definitions */
+/* FPB */
+#define FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR)
+#define FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR)
+#define FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0)
+#define FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1)
+#define FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2)
+#define FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3)
+#define FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4)
+#define FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5)
+#define FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6)
+#define FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7)
+#define FP_PID4 FPB_PID4_REG(FPB_BASE_PTR)
+#define FP_PID5 FPB_PID5_REG(FPB_BASE_PTR)
+#define FP_PID6 FPB_PID6_REG(FPB_BASE_PTR)
+#define FP_PID7 FPB_PID7_REG(FPB_BASE_PTR)
+#define FP_PID0 FPB_PID0_REG(FPB_BASE_PTR)
+#define FP_PID1 FPB_PID1_REG(FPB_BASE_PTR)
+#define FP_PID2 FPB_PID2_REG(FPB_BASE_PTR)
+#define FP_PID3 FPB_PID3_REG(FPB_BASE_PTR)
+#define FP_CID0 FPB_CID0_REG(FPB_BASE_PTR)
+#define FP_CID1 FPB_CID1_REG(FPB_BASE_PTR)
+#define FP_CID2 FPB_CID2_REG(FPB_BASE_PTR)
+#define FP_CID3 FPB_CID3_REG(FPB_BASE_PTR)
+
+/* FPB - Register array accessors */
+#define FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index)
+
+/*!
+ * @}
+ */ /* end of group FPB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FPB_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral FTFE
+ * @{
+ */
+
+/** FTFE - Peripheral register structure */
+typedef struct FTFE_MemMap {
+ uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} volatile *FTFE_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFE - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
+ * @{
+ */
+
+
+/* FTFE - Register accessors */
+#define FTFE_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFE_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFE_FSEC_REG(base) ((base)->FSEC)
+#define FTFE_FOPT_REG(base) ((base)->FOPT)
+#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFE_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFE_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFE_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFE_FPROT0_REG(base) ((base)->FPROT0)
+#define FTFE_FEPROT_REG(base) ((base)->FEPROT)
+#define FTFE_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFE Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFE_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFE_FSTAT_MGSTAT0_SHIFT 0
+#define FTFE_FSTAT_FPVIOL_MASK 0x10u
+#define FTFE_FSTAT_FPVIOL_SHIFT 4
+#define FTFE_FSTAT_ACCERR_MASK 0x20u
+#define FTFE_FSTAT_ACCERR_SHIFT 5
+#define FTFE_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFE_FSTAT_RDCOLERR_SHIFT 6
+#define FTFE_FSTAT_CCIF_MASK 0x80u
+#define FTFE_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFE_FCNFG_EEERDY_MASK 0x1u
+#define FTFE_FCNFG_EEERDY_SHIFT 0
+#define FTFE_FCNFG_RAMRDY_MASK 0x2u
+#define FTFE_FCNFG_RAMRDY_SHIFT 1
+#define FTFE_FCNFG_PFLSH_MASK 0x4u
+#define FTFE_FCNFG_PFLSH_SHIFT 2
+#define FTFE_FCNFG_SWAP_MASK 0x8u
+#define FTFE_FCNFG_SWAP_SHIFT 3
+#define FTFE_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFE_FCNFG_ERSSUSP_SHIFT 4
+#define FTFE_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFE_FCNFG_ERSAREQ_SHIFT 5
+#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFE_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFE_FCNFG_CCIE_MASK 0x80u
+#define FTFE_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFE_FSEC_SEC_MASK 0x3u
+#define FTFE_FSEC_SEC_SHIFT 0
+#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC)
+#define FTM_CNT_REG(base) ((base)->CNT)
+#define FTM_MOD_REG(base) ((base)->MOD)
+#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base) ((base)->CNTIN)
+#define FTM_STATUS_REG(base) ((base)->STATUS)
+#define FTM_MODE_REG(base) ((base)->MODE)
+#define FTM_SYNC_REG(base) ((base)->SYNC)
+#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base) ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
+#define FTM_POL_REG(base) ((base)->POL)
+#define FTM_FMS_REG(base) ((base)->FMS)
+#define FTM_FILTER_REG(base) ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
+#define FTM_CONF_REG(base) ((base)->CONF)
+#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR)
+#define I2S_TCR1_REG(base) ((base)->TCR1)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TFR_REG(base,index) ((base)->TFR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR1_REG(base) ((base)->RCR1)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RFR_REG(base,index) ((base)->RFR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+#define I2S_MDR_REG(base) ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<STIM_READ[index2])
+#define ITM_STIM_WRITE_REG(base,index2) ((base)->STIM_WRITE[index2])
+#define ITM_TER_REG(base) ((base)->TER)
+#define ITM_TPR_REG(base) ((base)->TPR)
+#define ITM_TCR_REG(base) ((base)->TCR)
+#define ITM_LAR_REG(base) ((base)->LAR)
+#define ITM_LSR_REG(base) ((base)->LSR)
+#define ITM_PID4_REG(base) ((base)->PID4)
+#define ITM_PID5_REG(base) ((base)->PID5)
+#define ITM_PID6_REG(base) ((base)->PID6)
+#define ITM_PID7_REG(base) ((base)->PID7)
+#define ITM_PID0_REG(base) ((base)->PID0)
+#define ITM_PID1_REG(base) ((base)->PID1)
+#define ITM_PID2_REG(base) ((base)->PID2)
+#define ITM_PID3_REG(base) ((base)->PID3)
+#define ITM_CID0_REG(base) ((base)->CID0)
+#define ITM_CID1_REG(base) ((base)->CID1)
+#define ITM_CID2_REG(base) ((base)->CID2)
+#define ITM_CID3_REG(base) ((base)->CID3)
+
+/*!
+ * @}
+ */ /* end of group ITM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ITM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ITM_Register_Masks ITM Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group ITM_Register_Masks */
+
+
+/* ITM - Peripheral instance base addresses */
+/** Peripheral ITM base pointer */
+#define ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u)
+/** Array initializer of ITM peripheral base pointers */
+#define ITM_BASE_PTRS { ITM_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- ITM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros
+ * @{
+ */
+
+
+/* ITM - Register instance definitions */
+/* ITM */
+#define ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0)
+#define ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0)
+#define ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1)
+#define ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1)
+#define ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2)
+#define ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2)
+#define ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3)
+#define ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3)
+#define ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4)
+#define ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4)
+#define ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5)
+#define ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5)
+#define ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6)
+#define ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6)
+#define ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7)
+#define ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7)
+#define ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8)
+#define ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8)
+#define ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9)
+#define ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9)
+#define ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10)
+#define ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10)
+#define ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11)
+#define ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11)
+#define ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12)
+#define ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12)
+#define ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13)
+#define ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13)
+#define ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14)
+#define ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14)
+#define ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15)
+#define ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15)
+#define ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16)
+#define ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16)
+#define ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17)
+#define ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17)
+#define ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18)
+#define ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18)
+#define ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19)
+#define ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19)
+#define ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20)
+#define ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20)
+#define ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21)
+#define ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21)
+#define ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22)
+#define ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22)
+#define ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23)
+#define ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23)
+#define ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24)
+#define ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24)
+#define ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25)
+#define ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25)
+#define ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26)
+#define ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26)
+#define ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27)
+#define ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27)
+#define ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28)
+#define ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28)
+#define ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29)
+#define ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29)
+#define ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30)
+#define ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30)
+#define ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31)
+#define ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31)
+#define ITM_TER ITM_TER_REG(ITM_BASE_PTR)
+#define ITM_TPR ITM_TPR_REG(ITM_BASE_PTR)
+#define ITM_TCR ITM_TCR_REG(ITM_BASE_PTR)
+#define ITM_LAR ITM_LAR_REG(ITM_BASE_PTR)
+#define ITM_LSR ITM_LSR_REG(ITM_BASE_PTR)
+#define ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR)
+#define ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR)
+#define ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR)
+#define ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR)
+#define ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR)
+#define ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR)
+#define ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR)
+#define ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR)
+#define ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR)
+#define ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR)
+#define ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR)
+#define ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR)
+
+/* ITM - Register array accessors */
+#define ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2)
+#define ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2)
+
+/*!
+ * @}
+ */ /* end of group ITM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ITM_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCDC
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDC_Peripheral LCDC
+ * @{
+ */
+
+/** LCDC - Peripheral register structure */
+typedef struct LCDC_MemMap {
+ uint32_t LSSAR; /**< LCDC screen start address register, offset: 0x0 */
+ uint32_t LSR; /**< LCDC size register, offset: 0x4 */
+ uint32_t LVPWR; /**< LCDC virtual page width register, offset: 0x8 */
+ uint32_t LCPR; /**< LCDC cursor position register, offset: 0xC */
+ uint32_t LCWHB; /**< LCDC cursor width, height, and blink register, offset: 0x10 */
+ uint32_t LCCMR; /**< LCDC color cursor mapping register, offset: 0x14 */
+ uint32_t LPCR; /**< LCDC panel configuration register, offset: 0x18 */
+ uint32_t LHCR; /**< LCDC horizontal configuration register, offset: 0x1C */
+ uint32_t LVCR; /**< LCDC vertical configuration register, offset: 0x20 */
+ uint32_t LPOR; /**< LCDC panning offset register, offset: 0x24 */
+ uint8_t RESERVED_0[4];
+ uint32_t LPCCR; /**< LCDC PWM contrast control register, offset: 0x2C */
+ uint32_t LDCR; /**< LCDC DMA control register, offset: 0x30 */
+ uint32_t LRMCR; /**< LCDC refresh mode control register, offset: 0x34 */
+ uint32_t LICR; /**< LCDC interrupt configuration register, offset: 0x38 */
+ uint32_t LIER; /**< LCDC interrupt enable register, offset: 0x3C */
+ uint32_t LISR; /**< LCDC interrupt status register, offset: 0x40 */
+ uint8_t RESERVED_1[12];
+ uint32_t LGWSAR; /**< LCDC graphic window start address register, offset: 0x50 */
+ uint32_t LGWSR; /**< LCDC graphic window size register, offset: 0x54 */
+ uint32_t LGWVPWR; /**< LCDC graphic window virtual page width register, offset: 0x58 */
+ uint32_t LGWPOR; /**< LCDC graphic window panning offset register, offset: 0x5C */
+ uint32_t LGWPR; /**< LCDC graphic window position register, offset: 0x60 */
+ uint32_t LGWCR; /**< LCDC graphic window control register, offset: 0x64 */
+ uint32_t LGWDCR; /**< LCDC graphic window DMA control register, offset: 0x68 */
+ uint8_t RESERVED_2[20];
+ uint32_t LAUSCR; /**< LCDC AUS mode control register, offset: 0x80 */
+ uint32_t LAUSCCR; /**< LCDC AUS mode cursor control register, offset: 0x84 */
+} volatile *LCDC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LCDC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDC_Register_Accessor_Macros LCDC - Register accessor macros
+ * @{
+ */
+
+
+/* LCDC - Register accessors */
+#define LCDC_LSSAR_REG(base) ((base)->LSSAR)
+#define LCDC_LSR_REG(base) ((base)->LSR)
+#define LCDC_LVPWR_REG(base) ((base)->LVPWR)
+#define LCDC_LCPR_REG(base) ((base)->LCPR)
+#define LCDC_LCWHB_REG(base) ((base)->LCWHB)
+#define LCDC_LCCMR_REG(base) ((base)->LCCMR)
+#define LCDC_LPCR_REG(base) ((base)->LPCR)
+#define LCDC_LHCR_REG(base) ((base)->LHCR)
+#define LCDC_LVCR_REG(base) ((base)->LVCR)
+#define LCDC_LPOR_REG(base) ((base)->LPOR)
+#define LCDC_LPCCR_REG(base) ((base)->LPCCR)
+#define LCDC_LDCR_REG(base) ((base)->LDCR)
+#define LCDC_LRMCR_REG(base) ((base)->LRMCR)
+#define LCDC_LICR_REG(base) ((base)->LICR)
+#define LCDC_LIER_REG(base) ((base)->LIER)
+#define LCDC_LISR_REG(base) ((base)->LISR)
+#define LCDC_LGWSAR_REG(base) ((base)->LGWSAR)
+#define LCDC_LGWSR_REG(base) ((base)->LGWSR)
+#define LCDC_LGWVPWR_REG(base) ((base)->LGWVPWR)
+#define LCDC_LGWPOR_REG(base) ((base)->LGWPOR)
+#define LCDC_LGWPR_REG(base) ((base)->LGWPR)
+#define LCDC_LGWCR_REG(base) ((base)->LGWCR)
+#define LCDC_LGWDCR_REG(base) ((base)->LGWDCR)
+#define LCDC_LAUSCR_REG(base) ((base)->LAUSCR)
+#define LCDC_LAUSCCR_REG(base) ((base)->LAUSCCR)
+
+/*!
+ * @}
+ */ /* end of group LCDC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCDC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCDC_Register_Masks LCDC Register Masks
+ * @{
+ */
+
+/* LSSAR Bit Fields */
+#define LCDC_LSSAR_SSA_MASK 0xFFFFFFFCu
+#define LCDC_LSSAR_SSA_SHIFT 2
+#define LCDC_LSSAR_SSA(x) (((uint32_t)(((uint32_t)(x))<PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+#define LLWU_RST_REG(base) ((base)->RST)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<PCCCR)
+#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR)
+#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR)
+#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR)
+#define LMEM_PCCRMR_REG(base) ((base)->PCCRMR)
+#define LMEM_PSCCR_REG(base) ((base)->PSCCR)
+#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR)
+#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR)
+#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR)
+#define LMEM_PSCRMR_REG(base) ((base)->PSCRMR)
+
+/*!
+ * @}
+ */ /* end of group LMEM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LMEM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Register_Masks LMEM Register Masks
+ * @{
+ */
+
+/* PCCCR Bit Fields */
+#define LMEM_PCCCR_ENCACHE_MASK 0x1u
+#define LMEM_PCCCR_ENCACHE_SHIFT 0
+#define LMEM_PCCCR_ENWRBUF_MASK 0x2u
+#define LMEM_PCCCR_ENWRBUF_SHIFT 1
+#define LMEM_PCCCR_INVW0_MASK 0x1000000u
+#define LMEM_PCCCR_INVW0_SHIFT 24
+#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
+#define LMEM_PCCCR_PUSHW0_SHIFT 25
+#define LMEM_PCCCR_INVW1_MASK 0x4000000u
+#define LMEM_PCCCR_INVW1_SHIFT 26
+#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
+#define LMEM_PCCCR_PUSHW1_SHIFT 27
+#define LMEM_PCCCR_GO_MASK 0x80000000u
+#define LMEM_PCCCR_GO_SHIFT 31
+/* PCCLCR Bit Fields */
+#define LMEM_PCCLCR_LGO_MASK 0x1u
+#define LMEM_PCCLCR_LGO_SHIFT 0
+#define LMEM_PCCLCR_CACHEADDR_MASK 0xFFCu
+#define LMEM_PCCLCR_CACHEADDR_SHIFT 2
+#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_C3_REG(base) ((base)->C3)
+#define MCG_C4_REG(base) ((base)->C4)
+#define MCG_C5_REG(base) ((base)->C5)
+#define MCG_C6_REG(base) ((base)->C6)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_ATCVH_REG(base) ((base)->ATCVH)
+#define MCG_ATCVL_REG(base) ((base)->ATCVL)
+#define MCG_C7_REG(base) ((base)->C7)
+#define MCG_C8_REG(base) ((base)->C8)
+#define MCG_C10_REG(base) ((base)->C10)
+#define MCG_C11_REG(base) ((base)->C11)
+#define MCG_C12_REG(base) ((base)->C12)
+#define MCG_S2_REG(base) ((base)->S2)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_CR_REG(base) ((base)->CR)
+#define MCM_ISCR_REG(base) ((base)->ISCR)
+#define MCM_ETBCC_REG(base) ((base)->ETBCC)
+#define MCM_ETBRL_REG(base) ((base)->ETBRL)
+#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
+#define MCM_FADR_REG(base) ((base)->FADR)
+#define MCM_FATR_REG(base) ((base)->FATR)
+#define MCM_FDR_REG(base) ((base)->FDR)
+#define MCM_PID_REG(base) ((base)->PID)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR)
+#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
+#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
+#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
+#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MPU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK 0x1u
+#define MPU_CESR_VLD_SHIFT 0
+#define MPU_CESR_NRGD_MASK 0xF00u
+#define MPU_CESR_NRGD_SHIFT 8
+#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<RESERVED_0[index])
+#define NFC_SRAM_B1_REG(base,index) ((base)->RESERVED_0[index+0x1000u])
+#define NFC_SRAM_B2_REG(base,index) ((base)->RESERVED_0[index+0x2000u])
+#define NFC_SRAM_B3_REG(base,index) ((base)->RESERVED_0[index+0x3000u])
+
+#define NFC_SRAM_B0(index) NFC_SRAM_B0_REG(NFC_BASE_PTR,index)
+#define NFC_SRAM_B1(index) NFC_SRAM_B1_REG(NFC_BASE_PTR,index)
+#define NFC_SRAM_B2(index) NFC_SRAM_B2_REG(NFC_BASE_PTR,index)
+#define NFC_SRAM_B3(index) NFC_SRAM_B3_REG(NFC_BASE_PTR,index)
+
+/** NFC - Peripheral register structure */
+typedef struct NFC_MemMap {
+ uint8_t RESERVED_0[16128];
+ uint32_t CMD1; /**< Flash command 1, offset: 0x3F00 */
+ uint32_t CMD2; /**< Flash command 2, offset: 0x3F04 */
+ uint32_t CAR; /**< Column address, offset: 0x3F08 */
+ uint32_t RAR; /**< Row address, offset: 0x3F0C */
+ uint32_t RPT; /**< Flash command repeat, offset: 0x3F10 */
+ uint32_t RAI; /**< Row address increment, offset: 0x3F14 */
+ uint32_t SR1; /**< Flash status 1, offset: 0x3F18 */
+ uint32_t SR2; /**< Flash status 2, offset: 0x3F1C */
+ uint32_t DMA1; /**< DMA channel 1 address, offset: 0x3F20 */
+ uint32_t DMACFG; /**< DMA configuration, offset: 0x3F24 */
+ uint32_t SWAP; /**< Cach swap, offset: 0x3F28 */
+ uint32_t SECSZ; /**< Sector size, offset: 0x3F2C */
+ uint32_t CFG; /**< Flash configuration, offset: 0x3F30 */
+ uint32_t DMA2; /**< DMA channel 2 address, offset: 0x3F34 */
+ uint32_t ISR; /**< Interrupt status, offset: 0x3F38 */
+} volatile *NFC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NFC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NFC_Register_Accessor_Macros NFC - Register accessor macros
+ * @{
+ */
+
+
+/* NFC - Register accessors */
+#define NFC_CMD1_REG(base) ((base)->CMD1)
+#define NFC_CMD2_REG(base) ((base)->CMD2)
+#define NFC_CAR_REG(base) ((base)->CAR)
+#define NFC_RAR_REG(base) ((base)->RAR)
+#define NFC_RPT_REG(base) ((base)->RPT)
+#define NFC_RAI_REG(base) ((base)->RAI)
+#define NFC_SR1_REG(base) ((base)->SR1)
+#define NFC_SR2_REG(base) ((base)->SR2)
+#define NFC_DMA1_REG(base) ((base)->DMA1)
+#define NFC_DMACFG_REG(base) ((base)->DMACFG)
+#define NFC_SWAP_REG(base) ((base)->SWAP)
+#define NFC_SECSZ_REG(base) ((base)->SECSZ)
+#define NFC_CFG_REG(base) ((base)->CFG)
+#define NFC_DMA2_REG(base) ((base)->DMA2)
+#define NFC_ISR_REG(base) ((base)->ISR)
+
+/*!
+ * @}
+ */ /* end of group NFC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NFC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NFC_Register_Masks NFC Register Masks
+ * @{
+ */
+
+/* CMD1 Bit Fields */
+#define NFC_CMD1_BYTE3_MASK 0xFF0000u
+#define NFC_CMD1_BYTE3_SHIFT 16
+#define NFC_CMD1_BYTE3(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+#define NV_FEPROT_REG(base) ((base)->FEPROT)
+#define NV_FDPROT_REG(base) ((base)->FDPROT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<ISER[index])
+#define NVIC_ICER_REG(base,index) ((base)->ICER[index])
+#define NVIC_ISPR_REG(base,index) ((base)->ISPR[index])
+#define NVIC_ICPR_REG(base,index) ((base)->ICPR[index])
+#define NVIC_IABR_REG(base,index) ((base)->IABR[index])
+#define NVIC_IP_REG(base,index) ((base)->IP[index])
+#define NVIC_STIR_REG(base,index) ((base)->STIR[index])
+
+/*!
+ * @}
+ */ /* end of group NVIC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NVIC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NVIC_Register_Masks NVIC Register Masks
+ * @{
+ */
+
+/* ISER Bit Fields */
+#define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
+#define NVIC_ISER_SETENA_SHIFT 0
+#define NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base pointer */
+#define OSC0_BASE_PTR ((OSC_MemMapPtr)0x40065000u)
+/** Peripheral OSC1 base pointer */
+#define OSC1_BASE_PTR ((OSC_MemMapPtr)0x400E5000u)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0_BASE_PTR, OSC1_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC0 */
+#define OSC0_CR OSC_CR_REG(OSC0_BASE_PTR)
+/* OSC1 */
+#define OSC1_CR OSC_CR_REG(OSC1_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral PDB
+ * @{
+ */
+
+/** PDB - Peripheral register structure */
+typedef struct PDB_MemMap {
+ uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
+ uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */
+ uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[4];
+ uint8_t RESERVED_0[160];
+ struct { /* offset: 0x150, array step: 0x8 */
+ uint32_t INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
+ uint32_t INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ uint32_t PODLY[4]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} volatile *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base) ((base)->SC)
+#define PDB_MOD_REG(base) ((base)->MOD)
+#define PDB_CNT_REG(base) ((base)->CNT)
+#define PDB_IDLY_REG(base) ((base)->IDLY)
+#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
+#define PDB_S_REG(base,index) ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base) ((base)->POEN)
+#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+#define PORT_DFER_REG(base) ((base)->DFER)
+#define PORT_DFCR_REG(base) ((base)->DFCR)
+#define PORT_DFWR_REG(base) ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_MR_REG(base) ((base)->MR)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR)
+#define RNG_SR_REG(base) ((base)->SR)
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_OR_REG(base) ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK 0x1u
+#define RNG_CR_GO_SHIFT 0
+#define RNG_CR_HA_MASK 0x2u
+#define RNG_CR_HA_SHIFT 1
+#define RNG_CR_INTM_MASK 0x4u
+#define RNG_CR_INTM_SHIFT 2
+#define RNG_CR_CLRI_MASK 0x8u
+#define RNG_CR_CLRI_SHIFT 3
+#define RNG_CR_SLP_MASK 0x10u
+#define RNG_CR_SLP_SHIFT 4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK 0x1u
+#define RNG_SR_SECV_SHIFT 0
+#define RNG_SR_LRS_MASK 0x2u
+#define RNG_SR_LRS_SHIFT 1
+#define RNG_SR_ORU_MASK 0x4u
+#define RNG_SR_ORU_SHIFT 2
+#define RNG_SR_ERRI_MASK 0x8u
+#define RNG_SR_ERRI_SHIFT 3
+#define RNG_SR_SLP_MASK 0x10u
+#define RNG_SR_SLP_SHIFT 4
+#define RNG_SR_OREG_LVL_MASK 0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT 8
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+#define RTC_TTSR_REG(base) ((base)->TTSR)
+#define RTC_MER_REG(base) ((base)->MER)
+#define RTC_MCLR_REG(base) ((base)->MCLR)
+#define RTC_MCHR_REG(base) ((base)->MCHR)
+#define RTC_WAR_REG(base) ((base)->WAR)
+#define RTC_RAR_REG(base) ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<ACTLR)
+#define SCB_CPUID_REG(base) ((base)->CPUID)
+#define SCB_ICSR_REG(base) ((base)->ICSR)
+#define SCB_VTOR_REG(base) ((base)->VTOR)
+#define SCB_AIRCR_REG(base) ((base)->AIRCR)
+#define SCB_SCR_REG(base) ((base)->SCR)
+#define SCB_CCR_REG(base) ((base)->CCR)
+#define SCB_SHPR1_REG(base) ((base)->SHPR1)
+#define SCB_SHPR2_REG(base) ((base)->SHPR2)
+#define SCB_SHPR3_REG(base) ((base)->SHPR3)
+#define SCB_SHCSR_REG(base) ((base)->SHCSR)
+#define SCB_CFSR_REG(base) ((base)->CFSR)
+#define SCB_HFSR_REG(base) ((base)->HFSR)
+#define SCB_DFSR_REG(base) ((base)->DFSR)
+#define SCB_MMFAR_REG(base) ((base)->MMFAR)
+#define SCB_BFAR_REG(base) ((base)->BFAR)
+#define SCB_AFSR_REG(base) ((base)->AFSR)
+#define SCB_CPACR_REG(base) ((base)->CPACR)
+
+/*!
+ * @}
+ */ /* end of group SCB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SCB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCB_Register_Masks SCB Register Masks
+ * @{
+ */
+
+/* ACTLR Bit Fields */
+#define SCB_ACTLR_DISMCYCINT_MASK 0x1u
+#define SCB_ACTLR_DISMCYCINT_SHIFT 0
+#define SCB_ACTLR_DISDEFWBUF_MASK 0x2u
+#define SCB_ACTLR_DISDEFWBUF_SHIFT 1
+#define SCB_ACTLR_DISFOLD_MASK 0x4u
+#define SCB_ACTLR_DISFOLD_SHIFT 2
+/* CPUID Bit Fields */
+#define SCB_CPUID_REVISION_MASK 0xFu
+#define SCB_CPUID_REVISION_SHIFT 0
+#define SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<DSADDR)
+#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
+#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
+#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
+#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
+#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
+#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
+#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
+#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
+#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
+#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
+#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
+#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
+#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
+#define SDHC_WML_REG(base) ((base)->WML)
+#define SDHC_FEVT_REG(base) ((base)->FEVT)
+#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
+#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
+#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
+#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
+#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT 2
+#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT6_REG(base) ((base)->SOPT6)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC1_REG(base) ((base)->SCGC1)
+#define SIM_SCGC2_REG(base) ((base)->SCGC2)
+#define SIM_SCGC3_REG(base) ((base)->SCGC3)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDH_REG(base) ((base)->UIDH)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+#define SIM_CLKDIV3_REG(base) ((base)->CLKDIV3)
+#define SIM_CLKDIV4_REG(base) ((base)->CLKDIV4)
+#define SIM_MCR_REG(base) ((base)->MCR)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR)
+#define SPI_TCR_REG(base) ((base)->TCR)
+#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base) ((base)->SR)
+#define SPI_RSER_REG(base) ((base)->RSER)
+#define SPI_PUSHR_REG(base) ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base) ((base)->POPR)
+#define SPI_TXFR0_REG(base) ((base)->TXFR0)
+#define SPI_TXFR1_REG(base) ((base)->TXFR1)
+#define SPI_TXFR2_REG(base) ((base)->TXFR2)
+#define SPI_TXFR3_REG(base) ((base)->TXFR3)
+#define SPI_RXFR0_REG(base) ((base)->RXFR0)
+#define SPI_RXFR1_REG(base) ((base)->RXFR1)
+#define SPI_RXFR2_REG(base) ((base)->RXFR2)
+#define SPI_RXFR3_REG(base) ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<CSR)
+#define SysTick_RVR_REG(base) ((base)->RVR)
+#define SysTick_CVR_REG(base) ((base)->CVR)
+#define SysTick_CALIB_REG(base) ((base)->CALIB)
+
+/*!
+ * @}
+ */ /* end of group SysTick_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SysTick Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SysTick_Register_Masks SysTick Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define SysTick_CSR_ENABLE_MASK 0x1u
+#define SysTick_CSR_ENABLE_SHIFT 0
+#define SysTick_CSR_TICKINT_MASK 0x2u
+#define SysTick_CSR_TICKINT_SHIFT 1
+#define SysTick_CSR_CLKSOURCE_MASK 0x4u
+#define SysTick_CSR_CLKSOURCE_SHIFT 2
+#define SysTick_CSR_COUNTFLAG_MASK 0x10000u
+#define SysTick_CSR_COUNTFLAG_SHIFT 16
+/* RVR Bit Fields */
+#define SysTick_RVR_RELOAD_MASK 0xFFFFFFu
+#define SysTick_RVR_RELOAD_SHIFT 0
+#define SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<SSPSR)
+#define TPIU_CSPSR_REG(base) ((base)->CSPSR)
+#define TPIU_ACPR_REG(base) ((base)->ACPR)
+#define TPIU_SPPR_REG(base) ((base)->SPPR)
+#define TPIU_FFSR_REG(base) ((base)->FFSR)
+#define TPIU_FFCR_REG(base) ((base)->FFCR)
+#define TPIU_FSCR_REG(base) ((base)->FSCR)
+#define TPIU_TRIGGER_REG(base) ((base)->TRIGGER)
+#define TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0)
+#define TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2)
+#define TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0)
+#define TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1)
+#define TPIU_ITCTRL_REG(base) ((base)->ITCTRL)
+#define TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET)
+#define TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR)
+#define TPIU_DEVID_REG(base) ((base)->DEVID)
+#define TPIU_PID4_REG(base) ((base)->PID4)
+#define TPIU_PID5_REG(base) ((base)->PID5)
+#define TPIU_PID6_REG(base) ((base)->PID6)
+#define TPIU_PID7_REG(base) ((base)->PID7)
+#define TPIU_PID0_REG(base) ((base)->PID0)
+#define TPIU_PID1_REG(base) ((base)->PID1)
+#define TPIU_PID2_REG(base) ((base)->PID2)
+#define TPIU_PID3_REG(base) ((base)->PID3)
+#define TPIU_CID0_REG(base) ((base)->CID0)
+#define TPIU_CID1_REG(base) ((base)->CID1)
+#define TPIU_CID2_REG(base) ((base)->CID2)
+#define TPIU_CID4_REG(base) ((base)->CID4)
+
+/*!
+ * @}
+ */ /* end of group TPIU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPIU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPIU_Register_Masks TPIU Register Masks
+ * @{
+ */
+
+
+/*!
+ * @}
+ */ /* end of group TPIU_Register_Masks */
+
+
+/* TPIU - Peripheral instance base addresses */
+/** Peripheral TPIU base pointer */
+#define TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u)
+/** Array initializer of TPIU peripheral base pointers */
+#define TPIU_BASE_PTRS { TPIU_BASE_PTR }
+
+/* ----------------------------------------------------------------------------
+ -- TPIU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros
+ * @{
+ */
+
+
+/* TPIU - Register instance definitions */
+/* TPIU */
+#define TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR)
+#define TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR)
+#define TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR)
+#define TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR)
+#define TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR)
+#define TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR)
+#define TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR)
+#define TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR)
+#define TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR)
+#define TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR)
+#define TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR)
+#define TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR)
+#define TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR)
+#define TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR)
+#define TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR)
+#define TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR)
+#define TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR)
+#define TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR)
+#define TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR)
+#define TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR)
+#define TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR)
+#define TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR)
+#define TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR)
+#define TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR)
+#define TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR)
+#define TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR)
+#define TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR)
+#define TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR)
+
+/*!
+ * @}
+ */ /* end of group TPIU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group TPIU_Peripheral */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral TSI
+ * @{
+ */
+
+/** TSI - Peripheral register structure */
+typedef struct TSI_MemMap {
+ uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} volatile *TSI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- TSI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros
+ * @{
+ */
+
+
+/* TSI - Register accessors */
+#define TSI_GENCS_REG(base) ((base)->GENCS)
+#define TSI_SCANC_REG(base) ((base)->SCANC)
+#define TSI_PEN_REG(base) ((base)->PEN)
+#define TSI_WUCNTR_REG(base) ((base)->WUCNTR)
+#define TSI_CNTR1_REG(base) ((base)->CNTR1)
+#define TSI_CNTR3_REG(base) ((base)->CNTR3)
+#define TSI_CNTR5_REG(base) ((base)->CNTR5)
+#define TSI_CNTR7_REG(base) ((base)->CNTR7)
+#define TSI_CNTR9_REG(base) ((base)->CNTR9)
+#define TSI_CNTR11_REG(base) ((base)->CNTR11)
+#define TSI_CNTR13_REG(base) ((base)->CNTR13)
+#define TSI_CNTR15_REG(base) ((base)->CNTR15)
+#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD)
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK 0x1u
+#define TSI_GENCS_STPE_SHIFT 0
+#define TSI_GENCS_STM_MASK 0x2u
+#define TSI_GENCS_STM_SHIFT 1
+#define TSI_GENCS_ESOR_MASK 0x10u
+#define TSI_GENCS_ESOR_SHIFT 4
+#define TSI_GENCS_ERIE_MASK 0x20u
+#define TSI_GENCS_ERIE_SHIFT 5
+#define TSI_GENCS_TSIIE_MASK 0x40u
+#define TSI_GENCS_TSIIE_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_SWTS_MASK 0x100u
+#define TSI_GENCS_SWTS_SHIFT 8
+#define TSI_GENCS_SCNIP_MASK 0x200u
+#define TSI_GENCS_SCNIP_SHIFT 9
+#define TSI_GENCS_OVRF_MASK 0x1000u
+#define TSI_GENCS_OVRF_SHIFT 12
+#define TSI_GENCS_EXTERF_MASK 0x2000u
+#define TSI_GENCS_EXTERF_SHIFT 13
+#define TSI_GENCS_OUTRGF_MASK 0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT 14
+#define TSI_GENCS_EOSF_MASK 0x8000u
+#define TSI_GENCS_EOSF_SHIFT 15
+#define TSI_GENCS_PS_MASK 0x70000u
+#define TSI_GENCS_PS_SHIFT 16
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_ED_REG(base) ((base)->ED)
+#define UART_MODEM_REG(base) ((base)->MODEM)
+#define UART_IR_REG(base) ((base)->IR)
+#define UART_PFIFO_REG(base) ((base)->PFIFO)
+#define UART_CFIFO_REG(base) ((base)->CFIFO)
+#define UART_SFIFO_REG(base) ((base)->SFIFO)
+#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816T0_REG(base) ((base)->WP7816T0)
+#define UART_WP7816T1_REG(base) ((base)->WP7816T1)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+#define UART_C6_REG(base) ((base)->C6)
+#define UART_PCTH_REG(base) ((base)->PCTH)
+#define UART_PCTL_REG(base) ((base)->PCTL)
+#define UART_B1T_REG(base) ((base)->B1T)
+#define UART_SDTH_REG(base) ((base)->SDTH)
+#define UART_SDTL_REG(base) ((base)->SDTL)
+#define UART_PRE_REG(base) ((base)->PRE)
+#define UART_TPL_REG(base) ((base)->TPL)
+#define UART_IE_REG(base) ((base)->IE)
+#define UART_WB_REG(base) ((base)->WB)
+#define UART_S3_REG(base) ((base)->S3)
+#define UART_S4_REG(base) ((base)->S4)
+#define UART_RPL_REG(base) ((base)->RPL)
+#define UART_RPREL_REG(base) ((base)->RPREL)
+#define UART_CPW_REG(base) ((base)->CPW)
+#define UART_RIDT_REG(base) ((base)->RIDT)
+#define UART_TIDT_REG(base) ((base)->TIDT)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base) ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base) ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL)
+#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
+#define USBDCD_STATUS_REG(base) ((base)->STATUS)
+#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
+#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
+#define USBDCD_TIMER2_REG(base) ((base)->TIMER2)
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<ID)
+#define USBHS_HWGENERAL_REG(base) ((base)->HWGENERAL)
+#define USBHS_HWHOST_REG(base) ((base)->HWHOST)
+#define USBHS_HWDEVICE_REG(base) ((base)->HWDEVICE)
+#define USBHS_HWTXBUF_REG(base) ((base)->HWTXBUF)
+#define USBHS_HWRXBUF_REG(base) ((base)->HWRXBUF)
+#define USBHS_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD)
+#define USBHS_GPTIMER0CTL_REG(base) ((base)->GPTIMER0CTL)
+#define USBHS_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD)
+#define USBHS_GPTIMER1CTL_REG(base) ((base)->GPTIMER1CTL)
+#define USBHS_USB_SBUSCFG_REG(base) ((base)->USB_SBUSCFG)
+#define USBHS_HCIVERSION_REG(base) ((base)->HCIVERSION)
+#define USBHS_HCSPARAMS_REG(base) ((base)->HCSPARAMS)
+#define USBHS_HCCPARAMS_REG(base) ((base)->HCCPARAMS)
+#define USBHS_DCIVERSION_REG(base) ((base)->DCIVERSION)
+#define USBHS_DCCPARAMS_REG(base) ((base)->DCCPARAMS)
+#define USBHS_USBCMD_REG(base) ((base)->USBCMD)
+#define USBHS_USBSTS_REG(base) ((base)->USBSTS)
+#define USBHS_USBINTR_REG(base) ((base)->USBINTR)
+#define USBHS_FRINDEX_REG(base) ((base)->FRINDEX)
+#define USBHS_DEVICEADDR_REG(base) ((base)->DEVICEADDR)
+#define USBHS_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE)
+#define USBHS_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR)
+#define USBHS_EPLISTADDR_REG(base) ((base)->EPLISTADDR)
+#define USBHS_TTCTRL_REG(base) ((base)->TTCTRL)
+#define USBHS_BURSTSIZE_REG(base) ((base)->BURSTSIZE)
+#define USBHS_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING)
+#define USBHS_ULPI_VIEWPORT_REG(base) ((base)->ULPI_VIEWPORT)
+#define USBHS_ENDPTNAK_REG(base) ((base)->ENDPTNAK)
+#define USBHS_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN)
+#define USBHS_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG)
+#define USBHS_PORTSC1_REG(base) ((base)->PORTSC1)
+#define USBHS_OTGSC_REG(base) ((base)->OTGSC)
+#define USBHS_USBMODE_REG(base) ((base)->USBMODE)
+#define USBHS_EPSETUPSR_REG(base) ((base)->EPSETUPSR)
+#define USBHS_EPPRIME_REG(base) ((base)->EPPRIME)
+#define USBHS_EPFLUSH_REG(base) ((base)->EPFLUSH)
+#define USBHS_EPSR_REG(base) ((base)->EPSR)
+#define USBHS_EPCOMPLETE_REG(base) ((base)->EPCOMPLETE)
+#define USBHS_EPCR0_REG(base) ((base)->EPCR0)
+#define USBHS_EPCR_REG(base,index) ((base)->EPCR[index])
+#define USBHS_USBGENCTRL_REG(base) ((base)->USBGENCTRL)
+
+/*!
+ * @}
+ */ /* end of group USBHS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHS_Register_Masks USBHS Register Masks
+ * @{
+ */
+
+/* ID Bit Fields */
+#define USBHS_ID_ID_MASK 0x3Fu
+#define USBHS_ID_ID_SHIFT 0
+#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x))<TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH)
+#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
+#define WDOG_WINH_REG(base) ((base)->WINH)
+#define WDOG_WINL_REG(base) ((base)->WINL)
+#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base) ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<